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Xilinx Zynq-7000 Design Manual

Xilinx Zynq-7000 Design Manual

All programmable soc pcb
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Zynq-7000
All Programmable SoC
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UG933 (v1.8) November 7, 2014

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Summary of Contents for Xilinx Zynq-7000

  • Page 1 Zynq-7000 All Programmable SoC PCB Design Guide UG933 (v1.8) November 7, 2014...

  • Page 2: Revision History

    Routing Topology section. Deleted SD/SDIO Peripheral Controller section. Added last sentence under sections SDIO and second sentence under QSPI. Added Chapter 6, Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 3 08/05/2014 1.7.1 Updated document to latest user guide template. 11/07/2014 Added XC7Z035 device to Table 3-1 Table 3-2. Added 10 Table 3-3. µF capacitor to Updated Table 5-5. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...

  • Page 4: Table Of Contents

    MIO/EMIO IP Layout Guidelines ........... . . 65 Zynq-7000 PCB Design Guide www.xilinx.com...

  • Page 5: Table Of Contents

    Xilinx Resources ........

  • Page 6: About This Guide

    (AP SoC), with a focus on strategies for making design decisions at the PCB and interface level. This Zynq-7000 All Programmable SoC PCB Design Guide, part of an overall set of documentation on the Zynq-7000 AP SoC, is available on the Xilinx website at www.xilinx.com/zynq.

  • Page 7: Introduction

    PCB; however, current technology places constraints and limits on the geometries and resulting electrical properties. The following information is provided as a guide to the freedoms, limitations, and techniques for PCB designs using Zynq-7000 AP SoC devices. This chapter contains the following sections: •...
  • Page 8 Where vias are not intended to make an electrical connection to the planes or planelets passed through, an antipad removes copper in the area of the layer where the via penetrates. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 9 Z-direction spacing of signal trace layers to reference plane layers affects signal trace impedance. Z-direction spacing of plane layers to other plane layers affects power system parasitic inductance. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...

  • Page 10: Transmission Lines

    Impedance variance can occur based on the presence or absence of glass in a local portion of the laminate weave, but this rarely poses issues except in high-speed (>6 Gb/s) interfaces. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...

  • Page 11: Return Currents

    They can also be a significant source of crosstalk and contributor to Power Distribution System (PDS) noise. The importance of return current paths cannot be underestimated. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 12 Power Distribution System Introduction This chapter documents the power distribution system (PDS) for Zynq-7000 AP SoC devices, including decoupling capacitor selection, placement, and PCB geometries. A simple decoupling method is provided for each device. Basic PDS design principles are covered, as well as simulation and analysis methods.
  • Page 13 Required PCB Capacitor Quantities Table 3-1 lists the PCB decoupling capacitor guidelines per V supply rail for Zynq-7000 AP SoC devices. Table 3-1: Required PCB Capacitor Quantities per Device (PL) (3)(4) per Bank...
  • Page 14 Z-7020 SBG485 Z-7030 FBG484/ Z-7030 RB484 FBG676 FFG676/ Z-7030 RF676 FBG676 Z-7035 FFG676/ Z-7035 RF676 FFG900/ Z-7035 RF900 FBG676 Z-7045 FFG676/ Z-7045 RF676 FFG900/ Z-7045 RF900 FFG900 Z-7100 Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 15 GRM188R60G106ME47 Ceramic X7R or X5R 4.7 µF C > 4.7 µF 0805 2-Terminal 0.5 nH 1 mΩ < ESR < 20 mΩ 6.3V GRM21BR71A475KA73 Ceramic X7R or X5R Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 16 The 4.7 µF capacitor covers the middle frequency range, while the 0.47 µF capacitor covers the high frequency range. Placement has some impact on performance. The 4.7 µF capacitors should be placed as close as possible to the AP SoC. Any placement within two Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...

  • Page 17: Basic Pds Principles

    In the same way that devices in a system have a requirement for the amount of current consumed by the power system, there is also a requirement for the cleanliness of the power. This cleanliness requirement specifies a maximum amount of noise present on the power Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 18 Chapter 3: Power Distribution System supply, often referred to as ripple voltage. Most digital devices, including all Zynq-7000 AP SoC devices, require that V supplies not fluctuate more than the specifications documented in the device data sheet. The power consumed by a digital device varies over time and this variance occurs on all frequency scales, creating a need for a wide-band PDS to maintain voltage stability.
  • Page 19 Inductance can be thought of as the momentum of charge. Charge moving through a conductor represents some amount of current. If the level of current changes, the charge Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 20 For larger values, such as 47 µF to 1000 µF, tantalum capacitors are usually used. These capacitors have a low parasitic inductance and a medium ESR, giving them a low Q factor and consequently a very wide range of effective frequencies. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 21 Because parasitic inductance for capacitors in a specific package is fixed, the inductance curve for capacitors in a specific package remains fixed. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 22 300 pH to 4 nH depending on the specific geometry. Because the current path’s inductance is proportional to the loop area the current traverses, it is important to minimize this loop size. The loop consists of the path through one power Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 23 The capacitor mounting (lands, traces, and vias) typically contributes about the same amount or more inductance than the capacitor's own parasitic self-inductance. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 24 However, because of the presence of substrate decoupling capacitors in Zynq-7000 AP SoC devices, there is a limit to the amount of fast transient current demanded from PCB decoupling capacitors.
  • Page 25 • and GND pins are distributed among the I/O pins. Every I/O pin in the Zynq-7000 AP SoC device pinout is adjacent to a return-current pin. AP SoC pinout arrangement determines the PCB via arrangement. The PCB designer cannot control the proximity of opposing current paths but has control over the trade-offs between the capacitor’s mounting inductance and AP SoC’s mounting inductance:...
  • Page 26 (Q) factor, and the Q factor can determine the width of the effective frequency band: • Tantalum capacitors generally have a very wide effective band. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 27 For example, using X7R Ceramic Chip capacitor in 0402 body size: C = 0.01 μF (selected by user) = 0.9 nH (capacitor data sheet parameter) SELF = 53 MHz (capacitor data sheet parameter) RSELF Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 28 To correct this type of problem, the characteristics of the high-frequency discrete capacitors or the characteristics of the V and ground planes must be changed, or AP SoC activity shifted to a different frequency away from the resonance. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 29 - - -- - -- - -- - - -- - -- - -- - -- - -- - -- - -- - - -- - -- - -- - -- - -- - -- - - -- - -- - -- - -- - -- - -- - - -- - -- - -- - -- - -- - -- - - -- - -- - -- - -- - -- - -- - -- - - - - Time Delay Equation 3-6 Signal propagation speed through FR4 dielectric The dielectric is the substrate of the PCB where the power planes are embedded. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 30 V supply. See DS187, Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and CCAUX Z-7020): DC and AC Switching Characteristics and DS191, Zynq-7000 All Programmable SoC (Z-7030, Z-7045, and Z-7100): DC and AC Switching Characteristics. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...

  • Page 31: Simulation Methods

    Table 3-5: EDA Tools for PDS Design and Simulation Tool Vendor Website URL Agilent http://www.agilent.com SIwave, HFSS Ansoft http://www.ansoft.com Specctraquest Power Integrity Cadence http://www.cadence.com Speed 2000, PowerSI, PowerDC Sigrity http://www.sigrity.com Hyperlynx PI Mentor http://www.mentor.com Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...

  • Page 32: Pds Measurements

    There are two basic ways of using the oscilloscope to view power system noise, each for a different purpose. The first surveys all possible noise events, while the second is useful for focusing on individual noise sources. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 33 I/O activity. Because the infinite persistence measurement catches all noise events over a long period, both correlated and non-correlated with the primary aggressor, all power system excursions are shown. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 34 A spectrum analyzer is a frequency-domain instrument, showing the frequency content of a voltage signal at its inputs. Using a spectrum analyzer, the user sees the exact frequencies where the PDS is inadequate. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 35 This isolates the spectrum analyzer from the device supply voltage. Figure 3-10 is an example of a noise spectrum measurement of the V power-supply noise, with multiple I/O sending patterns at 100 MHz. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 36 Z f ( ) From Network Analyzer Using the data sheet’s maximum voltage ripple value, the impedance value needed at all frequencies can be determined. This yields a target impedance as a function of frequency. A Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...

  • Page 37: Troubleshooting

    To reduce the current loop area, vias should be placed directly against capacitor solder lands. Never connect vias to the lands with a section of trace. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 38 Restrict signals to fewer routing layers with verified continuous return current paths. • Provide low-impedance paths for AC currents to travel between reference planes (high-frequency decoupling capacitors at PCB locations where layer transitions occur). Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 39 SelectIO Signaling Introduction The Zynq-7000 AP SoC SelectIO resources are the general-purpose I/O and its various settings. With numerous I/O standards and hundreds of variants within these standards, these SelectIO resources offer a flexible array of choices for designing I/O interfaces.

  • Page 40: Single-Ended Signaling

    SDR or DDR. Single-Ended Signaling A variety of single-ended I/O standards are available in the Zynq-7000 AP SoC I/O. For a complete list of supported I/O standards and detailed information about each one, refer to the “SelectIO Resources”...
  • Page 41 Topography generally refers to the arrangement of drivers, receivers, interconnect and terminations in an interface. The techniques used in unidirectional topographies are different from those used in bidirectional topographies, so these are treated separately. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 42 V voltage level, and VRN/VRP reference resistors for these terminations. X-Ref Target - Figure 4-1 = 50Ω = 25Ω = 50Ω UG933_c4_01_031711 Figure 4-1: Parallel-Terminated Unidirectional, Point-to-Point Topography Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 43 Thevenin parallel termination powered from 2.5V V , made up of two 100Ω resistors, resulting in a V of 1.25V and a parallel equivalent resistance (R ) of 50Ω . Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 44 There are a number of reasons why this selection might be advantageous in a given system. It is up to the designer to verify through simulation and measurement that the signal integrity at the receiver is adequate. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 45 50Ω transmission line, and the Thevenin parallel termination of two 100Ω resistors is on the right side. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 46 The two basic subsets of bidirectional topographies are point-to-point and multi-point. A point-to-point topography has two transceivers (driver and receiver sharing one device pin), while a multi-point topography can have many transceivers. Whether or not a Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback...
  • Page 47 Figure 4-7: Parallel Terminated Bidirectional Point-to-Point Topography X-Ref Target - Figure 4-8 = 25Ω 25Ω 25Ω 0 – 0 – = 50Ω = 25Ω UG933_c4_08_031711 Figure 4-8: Series Terminated Bidirectional Point-to-Point Topography: Not Recommended Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 48 (R ) of 50Ω . An example of the use of a controlled-impedance driver would be the LVDCI_15 I/O standard. By using 50Ω Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 49 I/O interface types that can be used with the bidirectional point-to-point topography. Table 4-3: Example I/O Interface Types for Bidirectional Point-to-Point I/O Topographies LVTTL LVCMOS LVDCI HSLVDCI SSTL15 Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 50 Because the Zynq-7000 AP SoC SSTL drivers target to have output impedances close to 40–50Ω, better signal integrity can be achieved without any external source-series termination.

  • Page 51: Power

    Chapter 5 Processing System (PS) Power and Signaling Power Zynq-7000 AP SoC devices are divided into several power domains. Figure 5-1 shows an overview of those domains. X-Ref Target - Figure 5-1 Processing System (PS) Programmable Logic (PL) CCPINT CCINT...
  • Page 52 10 µF capacitor – Murata GRM188R60G106ME47 • 0.47µF-4.7µF capacitor – Murata GRM155R60J474KE19 X-Ref Target - Figure 5-2 CCPAUX FERRITE-120 CCPLL 0.47-4.7 µF 10 µF UG933_c5_02_020813 Figure 5-2: Connecting V CCPLL Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 53 0.47 µF capacitor shall be added for decoupling. The PS DDR reference voltage can also be generated internally. For LPDDR2, PS_DDR_VREF0/1 shall be set to VDDq/2 in accordance with the HSUL_12 I/O standard. See section 2.5.7 (MIO Pin Electrical Parameters) in UG585, Zynq-7000 All Programmable SoC Technical Reference Manual. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 54 The I/O bank voltage is set by pulling pins MIO[7] and MIO[8] either High or Low. Table 5-3 shows the voltage mode configuration (VMODE) for MIO Bank 0 and Bank 1. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 55 If RGMII is not being used, PS_MIO_VREF is safe to float. Power Sequencing Refer to DS187, Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics and DS191, Zynq-7000 All Programmable SoC (Z-7030, Z-7045, and Z-7100): DC and AC Switching Characteristics for power supply sequencing requirements.

  • Page 56: Ps Clock And Reset

    LVCMOS signal, using the same voltage level as the V CCO_MIO0 voltage for bank MIO0. Refer to DS187, Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics and DS191, Zynq-7000 All Programmable SoC (Z-7030, Z-7045, and Z-7100): DC and AC Switching Characteristics for further PS_CLK requirements.

  • Page 57: Dynamic Memory

    Figure 5-4: Setting Mode Pins Dynamic Memory Zynq-7000 AP SoC devices support DDR2, DDR3/3L, and LPDDR2 (mobile DDR) dynamic memory. The memory is connected to dedicated pins in I/O Bank 502. This bank has dedicated I/O, termination, and reference voltage supplies.
  • Page 58 Connect to SDRAM Other IO Unconnected, internal pull-up by software Dynamic Memory Implementation Figure 5-5, Figure 5-6 Figure 5-7 show examples of implementing DDR memory on typical boards. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 59 (dq, dqs, dm) Data Group 3 Data Group (dq, dqs, dm) (dq, dqs, dm) Rvrnp Termination Regulator Rvrnp VDDQ VREF VREF VDDQ UG585_c30_04_022814 Figure 5-5: DDR3/3L Board Implementation Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 60 VDDQ VREF VDDQ VREF VDDQ VREF VDDQ Data Group 3 (dq, dqs, dm) VDDQ Rvrnp Termination Regulator VREF VDDQ VREF VDDQ Rvrnp UG933_c5_05_020614 Figure 5-6: DDR2 Board Implementation Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 61 IC. If a regulator is used, a low impedance plane or planelet is recommended for distribution. Table 5-6: DDR Voltage Voltage LPDDR2 DDR2 DDR3 DDR3L Comments LPDDR2 devices also require V (1.8V) and CCO_DDR 1.2V 1.8V 1.5V 1.35V (1.2V) Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 62 This feature is not supported on Zynq-7000 devices and those pins should be left floating. DDR Trace Length All DDR memory devices should be placed as closely to the Zynq-7000 AP SoC device as possible. Table 5-8 shows the maximum recommended trace lengths for DDR signals.
  • Page 63 Based on the chosen memory type, the number of memory devices and layout requirements, different routing topologies can be used for DDR memory. Figure 5-8 shows two different topologies. Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...
  • Page 64 LPDDR2 DDR2 DDR3/3L Devices Data Point-to-point Point-to-point Point-to-point Point-to-point Point-to-point Point-to-point Clock T-branch T-branch Fly-by T-branch Fly-by Point-to-point Point-to-point Point-to-point Address, Command, T-branch T-branch Fly-by/T-branch Control T-branch Fly-by/T-branch Zynq-7000 PCB Design Guide www.xilinx.com Send Feedback UG933 (v1.8) November 7, 2014...

  • Page 65: Mio/Emio Ip Layout Guidelines

    A 4.7 kΩ pull-up resistor shall be placed at the far end of the SCL and SDA lines, furthest from the Zynq-7000 AP SoC device. A level-shifter/repeater might be required depending on the particular multiplexers used. PCB and package delay skew for IIC_SDA to IIC_SCL should be less than ±500 ps.
  • Page 66 Chapter 5: Processing System (PS) Power and Signaling the Zynq-7000 AP SoC device and SD chip. PCB and package delay skew for SD_DAT[0:3] and SD_CMD relative to SD_CLK should be less than ±50 ps. Asynchronous signals SD_CDn and SD_WPn have no timing relationship to SD_CLK.
  • Page 67 (requirement) flash For example, with a Zynq-7000 AP SoC hold time requirement of 1.3 ns, and a flash clock-to-out of 1.0 ns, the propagation delay of the clock and data lines must be at least 0.15 ns. With a higher hold time requirement, the PCB trace delays will need to increase.
  • Page 68 For Fmax1, TQSPICKOMAX and TQSPIDCK are the respective clock-to-out and setup times of the Zynq-7000 AP SoC device. For Fmax2, Tckoflash and Tsuflash are the respective clock-to-out and setup times of the flash device, and Tpd is the maximum PCB propagation delay which includes Zynq device package propagation delay along with the flash package propagation delay.
  • Page 69 XC7Z015-CLG485 Devices Introduction Package migration across a device family is a common feature among Xilinx devices. The pinout remains consistent, with the biggest difference being more available I/Os in bigger packages. However, a unique case arises when migrating from an XC7Z030-SBG485 device to an XC7Z015-CLG485 device, as there are more significant differences between the devices other than pinout.
  • Page 70 For a general overview of Zynq-7000 devices as they pertain to Kintex-7 and Artix-7 device architectures, refer to the Zynq-7000 All Programmable SoC Overview (DS190). For more specific information regarding Kintex-7 and Artix-7 device architectures, refer to the Kintex-7 FPGAs Data Sheet (DS182), and the Artix-7 FPGAs Data Sheet (DS181).
  • Page 71 Software Considerations The Zynq-7000 XC7Z015 device is not supported in the ISE Design Suite and you should not use the Zynq-7000 XC7Z030 device in the SBG485 package in an attempt to migrate to a Zynq-7000 XC7Z015 device in the ISE Design Suite. You must use the Vivado Design Suite to migrate from the Zynq-7000 XC7Z030 device in the SBG485 package to the Zynq-7000 XC7Z015 device.

  • Page 72: Xilinx Resources

    Xilinx Support. • For continual updates, add the Answer Record to your myAlerts.. Device User Guides http://Zynq-7000 AP SoC Product Page http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm Xilinx Design Tools: Release Notes, Installation, and Licensing http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools. html Xilinx Forums and Wiki Links http://forums.xilinx.com ° http://wiki.xilinx.com °...

  • Page 73: Solution Centers

    UG821, Zynq-7000 All Programmable SoC Software Developers Guide ° UG585, Zynq-7000 All Programmable SoC Technical Reference Manual ° These user guides and additional relevant information can be found on the Xilinx Zynq-7000 AP SoC product page: http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_device s/soc/zynq-7000.html PL Documents – Device and Boards...
  • Page 74 UG873, Zynq-7000 All Programmable SoC: Concepts, Tools, and Techniques (CTT) The source drivers for stand alone and FSBL are provided as part of the Xilinx IDE Design Suite Embedded Edition. The Linux drivers are provided via the Xilinx Open Source Wiki at: http://wiki.xilinx.com...
  • Page 75 Xilinx Problem Solvers http://www.xilinx.com/support/troubleshoot.htm Third-Party IP and Standards Documents To learn about functional details related to vendor IP cores contained in Zynq-7000 devices or related international interface standards, refer the following documents: ARM documents can be found at: http://infocenter.arm.com/help/index.jsp...

  • Page 76: Please Read: Important Legal Notices

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 77 Appendix A: Additional Resources and Legal Notices terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos.

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