Xilinx Zynq-7000 User Manual page 368

Isolating Bit Errors
An important hardware debug step is to try to isolate when and where the bit errors occur.
Looking at the bit errors, these should be identified:
• Are errors seen on data bits belonging to certain CQ clock groups?
• Are errors seen on accesses to certain addresses of memory?
• Do the errors only occur for certain data patterns or sequences?
This can indicate a shorted or open connection on the PCB. This can also indicate an SSO or
crosstalk issue. It might be necessary to isolate whether the data corruption is due to writes
or reads. This case can be difficult to determine because if writes are the cause, read back
of the data is bad as well. In addition, issues with control or address timing affect both
writes and reads.
Some experiments that can be tried to isolate the issue are:
• If the errors are intermittent, have the design issue a small initial number of writes,
followed by continuous reads from those locations. If the reads intermittently yield bad
data, there is a potential read issue.
• Check/vary only write timing:
Check that the external termination resistors are populated on the PCB.
°
Use ODELAY to vary the phase of D relative to the K clocks.
°
• Vary only read timing:
Check the IDELAY values after calibration. Look for variations between IDELAY
°
values. IDELAY values should be very similar for Qs in the same CQS group.
Vary the IDELAY taps after calibration for the bits that are returning bad data.
°
This affects only the read capture timing.
Debugging the Core
The Debug port is a set of input and output signals that either provide status (outputs) or
allow you to make adjustments as the design is operating (inputs). When generating the
QDR II+ SRAM design through the MIG tool, an option is provided to turn the Debug Port
on or off. When the Debug port is turned off, the outputs of the debug port are still
generated but the inputs are ignored.
When the Debug port is turned on, the inputs are valid and must be driven to a logical
value. Driving the signals incorrectly on the debug port might cause the design to fail or
have less read data capture margin.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
www.xilinx.com
368
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