Xilinx Zynq-7000 User Manual page 135

The calibration stages in
• Memory Initialization, page 144
• PHASER_IN Phase Lock, page 145
• PHASER_IN DQSFOUND Calibration, page 145
• Write Leveling, page 146
• Multi-Purpose Register Read Leveling, page 149
• OCLKDELAYED Calibration, page 150
• Write Calibration, page 152
• Read Leveling, page 154
• PRBS Read Leveling, page 157
• Dynamic Calibration and Periodic Read Behavior, page 157
I/O Architecture
Each 7 series FPGA I/O bank has dedicated blocks comprising a PHY control block, four
PHASER_IN and PHASER_OUT blocks, four IN/OUT_FIFOs, ISERDES, OSERDES, ODDR,
IDELAY, and IOBs. A single PHY control block communicates with all four PHASER_IN and
PHASER_OUT blocks within the I/O bank.
PHY Control Block
The PHY control block is the central control block that manages the flow of data and control
information between the FPGA logic and the dedicated PHY. This includes control over the
flow of address, command, and data between the IN/OUT_FIFOs and ISERDES/OSERDES,
and control of the PHASER_IN and PHASER_OUT blocks. The PHY control block receives
control words from the calibration logic or the Memory Controller at the slow frequency
(1/4 the frequency of the DDR2 or DDR3 SDRAM clock) PHY_Clk rate and processes the
control words at the DDR2 or DDR3 SDRAM clock rate (CK frequency).
The calibration logic or the Memory Controller initiates a DDR2 or DDR3 SDRAM command
sequence by writing address, command, and data (for write commands) into the
IN/OUT_FIFOs and simultaneously or subsequently writes the PHY control word to the PHY
control block. The PHY control word defines a set of actions that the PHY control block does
to initiate the execution of a DDR2 or DDR3 SDRAM command.
The PHY control block provides the control interfaces to the byte group blocks within its I/O
bank. When multi-I/O bank implementations are required, each PHY control block within a
given I/O bank controls the byte group elements in that bank. This requires that the PHY
control blocks stay in phase with their adjacent PHY control blocks. The center PHY control
block is configured to be the master controller for a three I/O bank implementation. For two
bank implementations, either PHY control block can be designated the master.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-57 correspond to these sections:
www.xilinx.com
135
Send Feedback