Xilinx Zynq-7000 User Manual page 426

The core is composed of these elements, as shown in
• Client Interface
• Memory Controller
• Physical Interface
• Read Path
• Write Path
X-Ref Target - Figure 3-38
Client Interface
clk
sys_rst
user_cmd_en
user_rd_cmd
user_addr
user_ba
user_wr_en
user_wr_data
user_wr_dm
User Design
user_afifo_empty
user_afifo_aempty
user_afifo_full
user_afifo_afull
user_wdfifo_empty
user_wdfifo_aempty
user_wdfifo_full
user_wdfifo_afull
user_rd_valid
user_rd_data
init_calib_complete
Figure 3-38: Components of the RLDRAM II/RLDRAM 3 Memory Interface Solution
The client interface (also known as the user interface) uses a simple protocol based entirely
on SDR signals to make read and write requests. For more details describing this protocol,
see the Client Interface
The Memory Controller takes commands from the user interface and adheres to the
protocol requirements of the RLDRAM II/RLDRAM 3 device. For more information, see the
Memory Controller
The physical interface generates the proper timing relationships and DDR signaling to
communicate with the external memory device, while conforming to the
RLDRAM II/RLDRAM 3 protocol and timing requirements. For more details, see the
Interface section.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Infrastructure
User Interface
Write Path
byte_lane_
mapping
Read Path
section.
section.
www.xilinx.com
Figure 3-38:
Physical Interface
rld_ck_p
rld_ck_n
rld_dk_p
Memory Controller
rld_dk_n
rld_cs_n
rld_we_n
rld_ref_n
rld_a
rld_ba
rld_dm
rld_dq
rld_qk_p
rld_qk_n
rld_qvld
mc_phy
rld_reset_n
rld_phy_top
RLDRAM II/
RLDRAM 3 Device
UG586_c3_02_120411
Physical
426
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