Xilinx Zynq-7000 User Manual page 541

2. Click Out-of-Context Settings to configure generation of synthesized checkpoints. To
enable the Out-of-Context flow, enable the check box. To disable the Out-of-Context
flow, disable the check box. The default option is "enable" as shown in
X-Ref Target - Figure 4-28
3. MIG designs comply with "Hierarchical Design" flow in Vivado. For more information,
see the Vivado Design Suite User Guide: Hierarchical Design (UG905)
Vivado Design Suite Tutorial: Hierarchical Design (UG946)
4. After generating the MIG design, the project window appears as shown in
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Figure 4-28: Out-of-Context Settings Window
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Figure 4-28.
[Ref 5] and the
[Ref 6].
Figure
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