Xilinx Zynq-7000 User Manual page 59

example_design/rtl/traffic_gen
This directory contains the traffic generator that provides the stimulus to the
7 series FPGAs Memory Controller
Table 1-2: Files in example_design/rtl/traffic_gen Directory
(1)
Name
memc_traffic_gen.v
cmd_gen.v
cmd_prbs_gen.v
memc_flow_vcontrol.v
read_data_path.v
read_posted_fifo.v
rd_data_gen.v
write_data_path.v
wr_data_g.v
s7ven_data_gen.v
a_fifo.v
data_prbs_gen.v
init_mem_pattern_ctr.v
traffic_gen_top.v
Notes:
1. All file names are prefixed with the MIG core version number. For example, the MIG 4.1 release module name of
cmd_gen in generated output is now mig_7series_v4_1_cmd_gen.
<component name>/example_design/par
Table 1-3 lists the modules in the example_design/par directory.
Table 1-3: Files in example_design/par Directory
Name
example_top.xdc
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
(Table 1-2).
Description
This is the top-level of the traffic generator.
This is the command generator. This module provides
independent control of generating the types of commands,
addresses, and burst lengths.
This is a pseudo-random binary sequence (PRBS) generator for
generating PRBS commands, addresses, and burst lengths.
This module generates flow control logic between the Memory
Controller core and the cmd_gen, read_data_path, and
write_data_path modules.
This is the top-level for the read datapath.
This module stores the read command that is sent to the Memory
Controller, and its FIFO output is used to generate expect data for
read data comparisons.
This module generates timing control for reads and ready signals
to memc_flow_vcontrol.v.
This is the top-level for the write datapath.
This module generates timing control for writes and ready signals
to memc_flow_vcontrol.v.
This module generates different data patterns.
This is a synchronous FIFO using LUT RAMs.
This is a 32-bit linear feedback shift register (LFSR) for generating
PRBS data patterns.
This module generates flow control logic for the traffic generator.
This module is the top-level of the traffic generator and comprises
the memc_traffic_gen and init_mem_pattern_ctr modules.
Description
This is the XDC for the core and the example design.
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