Xilinx Zynq-7000 User Manual page 642

Table 4-28: 16-Bit LPDDR2 Interface Contained in One Bank (Cont'd)
Bank Signal Name
1
1 CKE
1 A12
1
1
1
1
1
1
1
1
1
1
1
1
1 VRN
CLOCK_DEDICATED_ROUTE Constraints
System Clock
If the SRCC/MRCC I/O pin and PLL are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint must be set to BACKBONE. LPDDR2 SDRAM manages
these constraints for designs generated with the System Clock option selected as
Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on the
SRCC/MRCC I/O and PLL allocation needs to be handled manually for the IP flow. LPDDR2
SDRAM does not generate clock constraints in the XDC file for the No Buffer
configurations. You must take care of the clock constraints for the No Buffer configurations
in the IP flow.
Reference Clock
If the SRCC/MRCC I/O pin and MMCM are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint is set to FALSE. Reference clock is a 200 MHz clock
source used to drive IODELAY CTRL logic (through an additional MMCM). This clock is not
utilized, CLOCK_DEDICADE_ROUTE (as they are limited in number), hence the FALSE value is
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Byte Group
– B_02
B_01
B_00
– A_11
– A_10
A9 A_09
A8 A_08
A7 A_07
A6 A_06
A5 A_05
A4 A_04
A3 A_03
A2 A_02
A1 A_01
A0 A_00
–
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
I/O Type I/O Number
N 15
P 14
N 13
P 12
N 11
P 10
N 9
P 8
N 7
P 6
N 5
P 4
N 3
P 2
N 1
SE 0
Special
Designation
–
–
–
–
–
–
–
DQS-P
DQS-N
–
–
–
–
–
–
–
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