Xilinx Zynq-7000 User Manual page 555

An FPGA byte lane should not contain pins related to two different strobe sets.
°
V I/O can be used only when the internal V
° REF
• Verified address pin rules:
Address signals cannot mix with data bytes.
°
It can use any number of isolated byte lanes.
°
Memory clock pins should be allocated to DQS I/O only.
°
Except memory clock pins, any other Address/Control pin should not be allocated
°
to DQS.
• Verified system pin rules:
System clock:
°
- These pins should be allocated to either SR/MR CC I/O pair.
- These pins must be allocated in the Memory banks column.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
Reference clock:
°
- These pins should be allocated to either SR/MR CC I/O pair.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
Status signals:
°
- The sys_rst signal should be allocated in the bank where the V
unallocated or the internal V
- These signals should be allocated in the non-memory banks because the I/O
standard is not compatible. The I/O standard type should be LVCMOS with at
least 1.8V.
- These signals can be allocated in any of the columns (there is no hard
requirement because these signals should reside in a memory column); however,
it is better to allocate closer to the chosen memory banks.
Quick Start Example Design
Overview
After the core is successfully generated, the example design HDL can be processed through
the Xilinx implementation toolset.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
is chosen.
REF
is used.
REF
www.xilinx.com
is used.
REF
is used.
REF
I/O is
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