Xilinx Zynq-7000 User Manual page 438

X-Ref Target - Figure 3-46
Figure 3-46: PHY-Only Interface for RLDRAM II Burst Length 4, Configuration 3, and Address
The controller sends the wr_en signals and data at the necessary time based on the
configuration setting. This time changes depending on the configuration.
when the wr_en signals should be asserted with the data valid for a given configuration. If
address multiplexing is used, the PHY handles rearranging the address signals and
outputting the address over two clock cycles rather than one.
Table 3-13: RLDRAM II Command to Write Enable Timing
Address Multiplexing
ON
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Multiplexing OFF
Command to Write
Configuration
Enable (Clock Cycles)
1
2
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Table 3-13
3
4
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