Xilinx Zynq-7000 User Manual page 470

• Read clocks (QK and QK#) need to be placed on the DQS pins that are available in a
data byte lane, respectively. Data must be in the same byte lane as the associated
QK/QK#.
• Address/control signals can be placed in byte groups that are not used for data and all
should be placed in the same bank. The address/control must be in the middle I/O
bank of the interfaces that span three I/O banks. Also, all address/control signals must
be in the same I/O bank. Address/control cannot be split between banks.
• For a given byte lane, the DQS_N location is used to generate the 3-state control signal.
The 3-state can share the location with DK# only
• The system clock input must be in the same column as the memory interface. The
system clock input is strongly recommended to be in the address/control bank. If this is
not possible, the system clock input must be in the bank above or below the
address/control bank.
RECOMMENDED:
(SLRs), it is not recommended due to the additional clock jitter in this topology.
• Devices implemented with SSI technology have SLRs. Memory interfaces cannot span
across SLRs. Ensure that this rule is followed for the part chosen and for any other
pin-compatible parts that can also be used.
System Clock, PLL Location, and Constraints
The PLL is required to be in the bank that supplies the clock to the memory to meet the
specified interface performance. The system clock input is also strongly recommended to
be in this bank. The MIG tool follows these two rules whenever possible. However,
exceptions are possible where pins might not be available for the clock input in the bank as
that of the PLL. In this case, the clock input needs to come from an adjacent bank through
the frequency backbone to the PLL. The system clock input to the PLL must come from
clock-capable I/Os.
The system clock input can only be used for an interface in the same column. The system
clock input cannot be driven from another column. The additional PLL or MMCM and clock
routing required for this induces too much additional jitter.
Unused outputs from the PLL can be used as clock outputs. Only the settings for these
outputs can be changed. Settings related to the overall PLL behavior and the used outputs
must not be disturbed. A PLL cannot be shared among interfaces.
See Clocking Architecture, page 434
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Although the MIG allows system clock selection to be in different super logic regions
for information on allowed PLL parameters.
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470
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