Appendix A: General Memory Routing Guidelines - Xilinx Zynq-7000 User Manual

7. Avoid routing over reference plane splits
X-Ref Target - Figure A-3
8. Keep the routing at least 30 mils away from the reference plane and void edges with the
exception of breakout regions
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Figure A-3: Signal Routing Over Reference Plane Split
(Figure
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Appendix A: General Memory Routing Guidelines
(Figure A-3).
UG583_c2_14_050614
A-2).
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