Xilinx Zynq-7000 User Manual page 220

Table 1-71: 64-Bit DDR3 Interface in Three Banks (Cont'd)
Bank Signal Name
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Byte Group
– A_00
VRN –
VRP –
– D_11
– D_10
– D_09
– D_08
– D_07
– D_06
– D_05
– D_04
– D_03
– D_02
– D_01
– D_00
– C_11
– C_10
– C_09
– C_08
– C_07
– C_06
– C_05
– C_04
– C_03
– C_02
– C_01
ODT C_00
RAS_N B_11
CAS_N B_10
WE_N B_09
BA2 B_08
CK_P B_07
CK_N B_06
BA1 B_05
www.xilinx.com
I/O Type I/O Number
N 1
SE 0
SE 49
P 48
N 47
P 46
N 45
P 44
N 43
P 42
N 41
P 40
N 39
P 38
N 37
P 36
N 35
P 34
N 33
P 32
N 31
P 30
N 29
P 28
N 27
P 26
N 25
P 24
N 23
P 22
N 21
P 20
N 19
P 18
Special
Designation
–
–
–
–
–
–
–
DQS-P
DQS-N
–
–
–
–
–
–
–
–
–
–
DQS-P
DQS-N
–
–
CCIO-P
CCIO-N
CCIO-P
CCIO-N
CCIO-P
CCIO-N
CCIO-P
CCIO-N
DQS-P
DQS-N
–
220
Send Feedback