Xilinx Zynq-7000 User Manual page 476

Table 3-22 shows the RLDRAM II byte lane with the 3-state pin location used for DM. In this
situation the signals are shifted down in the OUT_FIFO.
Table 3-22: Example RLDRAM II Byte Lane #5, Shared 3-State with DM in Byte Lane #2
Byte
Bank Lane Bit MAP
9 DQ26
8 DQ25
7 DQ24
6 DQ23
B DQ22
A DM
0 2
5 3-state
4 DQ21
3 DQ20
2 DQ19
1 DQ18
0
The byte lane parameters for
Table 3-23: Parameters for Example RLDRAM II Data Byte Lane #5
Parameter
DM_MAP
DQTS_MAP
PHY_0_BITLANES
DATA1_MAP
QK_MAP
I/O Standards
The MIG tool generates the appropriate XDC for the core with SelectIO™ standards based
on the type of input or output to the 7 series FPGAs. These standards should not be
changed. Table 3-24
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Byte I/O
DDR
Group Type
XDC
DQ26 C_11 P
DQ25 C_10 N
DQ24 C_09 P
DQ23 C_08 N
DQ22 C_07 P
DM C_06 N
DQ21 C_05 P
DQ20 C_04 N
DQ19 C_03 P
DQ18 C_02 N
QK1_P C_01 P
QK1_N C_00 N
Table 3-22 are shown in
Value
12'h02A
12'h025
12'hFDE
108'h029_028_027_026_02B_024_023_022_021
8'h02
and Table 3-25 contain a list of the ports with the I/O standard used.
www.xilinx.com
I/O Special
Number Designation
12
11
10
9
8 DQS-P
7 DQS-N
6
5
4 CCIO-P
3 CCIO-N
2 CCIO-P
1 CCIO-N
Table 3-23.
BITLANES
1
1
1
1
1 1111
1 F
110
0
1
1 D
1
1
111
1
0
0 E FDE
476
Send Feedback