Xilinx Zynq-7000 User Manual page 548

mig_7series_v4_1
docs
example_design
par
rtl
sim
synth
user_design
rtl
xdc
Directory and File Contents
The 7 series FPGAs core directories and their associated files are listed in this section for
Vivado implementations.
<component name>/example_design/
The example_design folder contains four folders, namely, par, rtl, sim, and synth.
example_design/rtl
This directory contains the example design
Table 4-1: Files in example_design/rtl Directory
Name
example_top.v
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
traffic_gen
clocking
controller
ip_top
phy
ui
Description
This top-level module serves as an example for connecting the user
design to the 7 series FPGAs memory interface core.
www.xilinx.com
(Table 4-1).
548
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