Xilinx Zynq-7000 User Manual page 377

Table 2-21: Read Stage 2 Debug Signal Map (Cont'd)
Bits
dbg_stage2_cal[10]
dbg_stage2_cal[11]
dbg_stage2_cal[12]
dbg_stage2_cal[13]
dbg_stage2_cal[14]
dbg_stage2_cal[15]
dbg_stage2_cal[16]
dbg_stage2_cal[17]
dbg_stage2_cal[18]
dbg_stage2_cal[19]
dbg_stage2_cal[20]
dbg_stage2_cal[21]
dbg_stage2_cal[22]
dbg_stage2_cal[25:23]
dbg_stage2_cal[26]
dbg_stage2_cal[29:27]
dbg_stage2_cal[30]
dbg_stage2_cal[31]
dbg_stage2_cal[32]
dbg_stage2_cal[33]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
PHY Signal Name
edge_adv_cal_start
rd0_vld
fd0_vld
rd1_vld
fd1_vld
phase_vld
rd0_bslip_vld
fd0_bslip_vld
rd1_bslip_vld
fd1_bslip_vld
phase_bslip_vld
clkdiv_phase_cal_done_4r
pi_edge_adv
byte_cnt[2:0]
inc_byte_cnt
pi_edge_adv_wait_cnt
bitslip
rd2_vld
fd2_vld
rd3_vld
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Chapter 2: QDR II+ Memory Interface Solution
Description
Indicates start of edge_adv calibration, to see if the
pi_edge_adv signal needs to be asserted
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
Valid data is seen for the particular byte for the byte being
calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data requiring bitslip for the
byte being calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data requiring bitslip for the
byte being calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data requiring bitslip for the
byte being calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data requiring bitslip for the
byte being calibrated (indicated by byte_cnt)
Valid data is seen when bitslip applied to read data for the
byte being calibrated (indicated by byte_cnt)
Indicates data validity complete, proceed to assert the
pi_edge_adv signal if needed
Phaser control signal to advance the Phaser clock, ICLKDIV
by one fast clk cycle. Only used for nCK_PER_CLK == 2.
Indicates the byte that is being checked for data validity
Internal signal to increment to the next byte
Counter to wait between asserting the phaser control
signal, pi_edge_adv signal in the various byte lanes.
FPGA logic bitslip control signal, indicates when the logic
shifts the data alignment. Only used for nCK_PER_CLK ==
4.
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt). Only valid for
nCK_PER_CLK == 4.
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt). Only valid for
nCK_PER_CLK == 4.
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt). Only valid for
nCK_PER_CLK == 4.
377
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