Xilinx Zynq-7000 User Manual page 394

The Mode register value is loaded into the Load Mode register during initialization.
• Input Clock Period – The desired input clock period is selected from the list. These
values are determined by the chosen memory clock period and the allowable limits of
the PLL parameters. See
PLL parameter limits.
• Configuration – (RLDRAM II only). This option sets the configuration value associated
with write and read latency values. Available values of 1, 2, and 3 are controlled based
on the selected design frequency.
• Burst Length – This option sets the length of a burst for a single memory transaction.
This option is a trade-off between granularity and bandwidth and should be
determined based on the application. Values of 4 and 8 are available for RLDRAM II,
and 2, 4, and 8 are allowed for RLDRAM 3.
• Address Multiplexing – This option minimizes the number of address pins required for
a design, because the address is provided using less pins but over two consecutive
clock cycles. This option is not supported with a burst length of two.
• Impedance Matching – This option determines how the memory device tunes its
outputs, either by an internal setting or using an external reference resistor connected
to the ZQ input of the memory device.
• On-Die Termination – This option is used to apply termination to the DQ and DM
signals at the memory device during write operations. When set, the memory device
dynamically switches off ODT when driving the bus during a read command. For
RLDRAM II this can only be off or on, but for RLDRAM 3 when a value must be selected,
either RZQ/6, RZQ/4, or RZQ/2.
• Output Driver Impedance Control – Not available for RLDRAM II. MRS setting in the
DRAM that selects the impedance of the output buffers during reads.
Click Next to display the FPGA Options page.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Clocking Architecture, page 434
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