Xilinx Zynq-7000 User Manual page 459

Table 3-14: RLDRAM II Memory Interface Solution Configurable Parameters (Cont'd)
Parameter
DATA_WIDTH
QK_WIDTH
DK_WIDTH
BURST_LEN
DM_PORT
NUM_DEVICES
MRS_CONFIG
MRS_ADDR_MUX
MRS_DLL_RESET
MRS_IMP_MATCH
MRS_ODT
MRS_RD_LATENCY
MRS_RTT_WR
MRS_RTT_RD
MEM_TRC
MEM_TYPE
(1)
IODELAY_GRP
REFCLK_FREQ
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Description
Memory data bus width and can be set through the MIG
tool. A maximum DATA_WIDTH of 72 is supported.
Memory read clock bus width.
Memory write clock bus width.
Memory data burst length.
This parameter enables and disables the generation of the
data mask ports.
Number of memory devices used.
This parameter sets the configuration setting in the
RLDRAM II/RLDRAM 3 memory register.
This parameter sets the address multiplexing setting in the
RLDRAM II/RLDRAM 3 memory register.
This parameter sets the DLL setting in the
RLDRAM II/RLDRAM 3 memory register.
This parameter sets the impedance setting in the memory
register.
This parameter sets the ODT setting in the memory
register.
This parameter sets the Read latency and write latency
setting in the RLDRAM 3 memory register, and is
dependent on memory device and frequency of operation.
This parameter sets the output drive impedance setting in
the MRS register for RLDRAM 3.
This parameter sets the ODT setting in the MRS register for
RLDRAM 3. If ODT is not used this parameter becomes a
"Do not care."
This parameter sets the RLDRAM 3 TRC setting, and is
dependent on the memory device and read latency
selected.
This parameter specifies the memory type.
This is a unique name for the IODELAY_CTRL provided
when multiple IP cores are used in the design.
Reference clock frequency for IDELAYCTRLs. This
parameter should not be changed.
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Options
–
RLDRAM II: 2 per
x18/x36 device
RLDRAM 3:
DATA_WIDTH/9
RLDRAM II: 2 per x36
device, 1 per x18
device
RLDRAM 3: 2 per
device
RLDRAM II: 4, 8
RLDRAM 3: 2, 4, 8
ON, OFF
1–4
RLDRAM II: 1, 2, 3
RLDRAM 3: 3, 4, 5, 6, 7,
8, 9, 10, 11
ON, OFF
DLL_ON
INTERNAL, EXTERNAL
ON, OFF
8–16
40, 60, 120
40, 60
4–11
RLD2_CIO, RLD3
–
200.0
459
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