Xilinx Zynq-7000 User Manual page 603

X-Ref Target - Figure 4-52
Out_Burst_Pending[3]
Out_Rank_D[1:0]
Freq_Ref_Clk
PHY_OF_AlmostFull
PHY_OF_Full
PHY_DM[1:0],
PHY_D_Out[15:0]
PHY_Clk
PHY_WrEn
PHY_D_In[15:0]
In_Burst_Pending[3]
In_Rank_D[1:0]
Out_Burst_Pending[2]
Out_Rank_C[1:0]
PC_Enable_Calib[1:0]
In_Burst_Pending[2]
In_Rank_C[1:0]
Each IN/OUT_FIFO has a storage array of memory elements arranged as 10 groups
eight bits wide and eight entries deep. During a write, the OUT_FIFO receives four bits of
data for each DQ bit from the calibration logic or Memory Controller and writes the data
into the storage array in the PHY_Clk clock domain, which is 1/2 the frequency of the
LPDDR2 SDRAM clock.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Data Byte Group D
Enable_Calib[1:0] OClk1x
Burst_Pending OClk1x90
RankSel[1:0] OClkDiv
Phaser
DQS[1:0]
Out D
PhaseRef
CTS[1:0]
DTS[1:0]
FreqRef
RdEnable
Out_FIFO_D
D Q
OF_RE_D
In_FIFO_D
Q D
IF_WE_D
1'b1
tied to 1
Enable_Calib[1:0]
Burst_Pending
RankSel[1:0] IClk1x
Phaser
IClkDiv
In D
PhaseRef RClk
FreqRef WriteEnable
Data Byte Group C
Enable_Calib[1:0] OClk1x
Burst_Pending OClk1x90
RankSel[1:0] OClkDiv
Phaser
DQS[1:0]
Out C
PhaseRef
CTS[1:0]
DTS[1:0]
FreqRef
RdEnable
Out_FIFO_C
D Q
OF_RE_C
In_FIFO_C
Q D
IF_WE_C
1'b1
tied to 1
Enable_Calib[1:0]
Burst_Pending
RankSel[1:0] IClk1x
Phaser
IClkDiv
In C
PhaseRef RClk
FreqRef WriteEnable
Figure 4-52: Datapath Block Diagram
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Note: CKE is implemented as a SDR
OFF clocked by DDR_Clk
OBUF
DDR_CKE
OFF
DDR_DivR_Clk
DQS_D
DQSTriState_D
OBUF
DQTriState_D
OSERDES
D_Out[15:8], DM1
WrBClk_D Byte Group
WrBClk_90_D
WrDivBClk_D
DQS_In_1
IBUF
ISERDES
D_In[15:8]
Byte Group
RdBClk_D
RdDivBClk_D
Note: RESET_N is implemented as a
SDR OFF clocked by DDR_Clk
OBUF
DDR_RESET_N
OFF
DDR_DivR_Clk
DQS_C
DQSTriState_C
OBUF
DQTriState_C
OSERDES
D_Out[7:0], DM0
Byte Group
WrBClk_C
WrBClk_90_C
WrDivBClk_C
DQS_In_0
IBUF
ISERDES
D_In[7:0]
Byte Group
RdBClk_C
RdDivBClk_C
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