Xilinx Zynq-7000 User Manual page 187

Table 1-65: Embedded 7 Series FPGAs Memory Solution Configuration Parameters (Cont'd)
Parameter
CLKOUT0_PHASE
DIVCLK_DIVIDE
USE_DM_PORT
CK_WIDTH
DQ_CNT_WIDTH
DRAM_TYPE
DRAM_WIDTH
AL
(1)
nBANK_MACHS
DATA_BUF_ADDR_WIDTH
SLOT_0_CONFIG
ECC
RANKS
DATA_WIDTH
APP_DATA_WIDTH
APP_MASK_WIDTH
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
–
–
This is the enable data mask option used
during memory write operations.
This is the number of CK/CK# outputs to
memory.
This is ceil(log2(DQ_WIDTH)).
This is the supported memory standard for
the Memory Controller.
This is the DQ bus width per DRAM
component.
This is the additive latency.
This is the number of bank machines. A
given bank machine manages a single
DRAM bank at any given time.
This is the bus width of the request tag
passed to the Memory Controller. This
parameter is set to 5 for 4:1 mode and 4 for
2:1 mode. This parameter should not be
changed.
This is the rank mapping. This parameter
should not be changed.
This is the error correction code, available in
72-bit data width configurations. ECC is not
currently available.
This is the number of ranks.
This parameter determines the write data
mask width and depends on whether or not
ECC is enabled.
This UI_INTFC parameter specifies the
payload data width in the UI.
This UI_INTFC parameter specifies the
payload mask width in the UI.
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Options
Phase of PLL output CLKOUT0. This
value is set by the MIG tool based
on the banks selected for memory
interface pins and the frequency of
operation.
PLLE2 VCO divisor. This value is set
by the MIG tool based on the
frequency of operation.
0 = Disable
1 = Enable
"DDR3", "DDR2"
0
2, 3, 4, 5, 6, 7, 8
5, 4
Single-rank setting: 8'b0000_0001
Dual-rank setting: 8'b0000_0011
72
ECC = ON:
DATA_WIDTH = DQ_WIDTH +
ECC_WIDTH
ECC = OFF:
DATA_WIDTH = DQ_WIDTH
APP_DATA_WIDTH =
2 x nCK_PER_CLK x PAYLOAD_WIDTH
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