Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
X-Ref Target - Figure 3-37
Figure 3-37: High-Level Block Diagram of RLDRAM II/RLDRAM 3 Interface Solution
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
425
Send Feedback
UG586 November 30, 2016
www.xilinx.com
Need help?
Do you have a question about the Zynq-7000 and is the answer not in the manual?
Questions and answers