Xilinx Zynq-7000 User Manual page 210

These rules indicate the maximum electrical delays between DDR2 SDRAM signals:
• The maximum electrical delay between any DQ or DM and its associated DQS/DQS# must
be ≤ ±5 ps.
• The maximum electrical delay between any address and control signals and the
corresponding CK/CK# must be ≤ ±25 ps.
• The maximum electrical delay between any DQS/DQS# and CK/CK# must be < ±25 ps.
Clocking
The 7 series FPGA MIG DDR3/DDR2 design has two clock inputs, the reference clock and the
system clock. The reference clock drives the IODELAYCTRL components in the design, while
the system clock input is used to create all MIG design clocks that are used to clock the
internal logic, the frequency reference clocks to the phasers, and a synchronization pulse
required for keeping PHY control blocks synchronized in multi-I/O bank implementations.
For more information on clocking architecture, see
The MIG tool allows you to input the Memory Clock Period and then lists available Input
Clock Periods that follow the supported clocking guidelines. Based on these two clock
periods selections, the generated MIG core appropriately sets the PLL parameters. The MIG
tool enables automatic generation of all supported clocking structures. For information on
how to use the MIG tool to set up the desired clocking structure including input clock
placement, input clock frequency, and IDELAYCTRL ref_clk generation, see
Series FPGA DDR3 Memory Controller Block Design, page
Input Clock Guidelines
The input system clock cannot be generated internally.
IMPORTANT:
• PLL Guidelines
CLKFBOUT_MULT_F (M) must be between 1 and 16 inclusive.
°
DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the PLLE2
°
parameter.
CLKOUT_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4
°
for below 400 MHz operation.
The above settings must ensure the minimum PLL VCO frequency (FVCOMIN) is
°
met. For specifications, see the appropriate DC and Switching Characteristics Data
Sheet. The 7 Series FPGAs Clocking Resources User Guide (UG472)
the equation for calculating FVCO.
The relationship between the input period and the memory period is InputPeriod =
°
(MemoryPeriod × M)/(D × D1).
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Clocking Architecture, page
www.xilinx.com
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