Xilinx Zynq-7000 User Manual page 396

If the designs generated from MIG for the No Buffer option are implemented without
performing changes, designs can fail in implementation due to IBUFs not instantiated
for the ref_clk_i signal. So for No Buffer scenarios, ref_clk_i signal needs to be
connected to an internal clock.
• System Reset Polarity – The polarity for system reset (sys_rst) can be selected. If the
option is selected as active-Low, the parameter RST_ACT_LOW is set to 1 and if set to
active-High the parameter RST_ACT_LOW is set to 0.
• Debug Signals Control – Selecting this option enables calibration status and user port
signals to be port mapped to the ILA and VIO in the example_top module. This helps
in monitoring traffic on the user interface port with the Vivado Design Suite debug
feature. Deselecting the Debug Signals Control option leaves the debug signals
unconnected in the example_top module and no ILA/VIO modules are generated by
the IP catalog. Additionally, the debug port is always disabled for functional
simulations.
• Sample Data Depth – This option selects the Sample Data depth for the ILA module
used in the Vivado debug logic. This option can be selected when the Debug Signals
for Memory Controller option is ON.
• Internal V
REF
use of the V
rates of 800 Mb/s or below.
Click Next to display the Extended FPGA Options page.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Selection – Internal V
pins for normal I/O usage. Internal V
REF
www.xilinx.com
can be used for data group bytes to allow the
REF
should only be used for data
REF
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