Xilinx Zynq-7000 User Manual page 413

Memory interface solutions
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Table 3-3: Files in example_design/sim Directory (Cont'd)
Name
sim_tb_top.v
Notes:
1. The ies_run.sh and vcs_run.sh files are generated in the folder mig_7series_0_ex/imports when the example
design is created using Open IP Example Design for the design generated with Component Name entered in
Vivado IDE as mig_7series_0.
<component name>/user_design/
The user_design folder contains the following:
rtl and xdc folders
Top-level wrapper module <component_name>.v/vhd
Top-level modules <component_name>_mig.v/vhd and
<component_name>_mig_sim.v/vhd
The top-level wrapper file <component_name>.v/vhd has an instantiation of top-level
file <component_name>_mig.v/vhd. Top-level wrapper file has no parameter
declarations and all the port declarations are of fixed width.
Top-level files <component_name>_mig.v/vhd and
<component_name>_mig_sim.v/vhd have the same module name as
<component_name>_mig. These two files are same in all respects except that the file
<component_name>_mig_sim.v/vhd has parameter values set for simulation where
calibration is in fast mode viz., SIM_BYPASS_INIT_CAL = "FAST" etc.
The top-level file <component_name>_mig.v/vhd is used for design synthesis and
IMPORTANT:
implementation, whereas the top-level file <component_name>_mig_sim.v/vhd is used in
simulations.
The top-level wrapper file serves as an example for connecting the user_design to the
7 series FPGA memory interface core.
user_design/rtl/controller
Table 3-4
lists the files in the user_design/rtl/controller directory.
Table 3-4: Files in user_design/rtl/controller Directory
(1)
Name
rld_mc.v
Notes:
1. All file names are prefixed with MIG version number. For example, for the MIG 4.1 release module name of
rld_mc in generated output is now mig_7series_v4_1_rld_mc.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Description
This file is the simulation top-level file.
Description
This module implements the Memory Controller.
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