Xilinx Zynq-7000 User Manual page 640

• Interfaces in Single I/O Column – If the memory interfaces are entirely contained
within the same I/O column, a common sys_clk can be shared among the interfaces.
The sys_clk can be input on any CCIO in the column where the memory interfaces are
located. This includes CCIO in banks that do not contain the memory interfaces, but
must be in the same column as the memory interfaces.
Information on Sharing BUFG Clock (phy_clk)
The MIG 7 series LPDDR2 SDRAM design includes a PLL which outputs the phy_clk on a
BUFG route. It is not possible to share this clock amongst multiple controllers to
synchronize the user interfaces. This is not allowed because the timing from the FPGA logic
to the PHY Control block must be controlled. This is not possible when the clock is shared
amongst multiple controllers. The only option for synchronizing user interfaces amongst
multiple controllers is to create an asynchronous FIFO for clock domain transfer.
Information on Sync_Pulse
The MIG 7 series LPDDR2 SDRAM design includes one MMCM that generates the necessary
design clocks. One of these outputs is the sync_pulse. The sync pulse clock is 1/16 of the
mem_refclk frequency and must have a duty cycle distortion of 1/16 or 6.25%. This clock
is distributed across the low skew clock backbone and keeps all PHASER_IN/_OUT and
PHY_Control blocks in sync with each other. The signal is sampled by the mem_refclk in
both the PHASER_INs/_OUTs and PHY_Control blocks. The phase, frequency, and duty cycle
of the sync_pulse is chosen to provide the greatest setup and hold margin across PVT.
LPDDR2 Pinout Examples
Table 4-28 shows an example of a 16-bit LPDDR2 interface contained within one bank. This
example is for a component interface using a 1 Gb x16 part. If x8 components are used or
a higher density part is needed that would require more address pins, these options are
possible:
• An additional bank can be used.
• RESET_N can be moved to another bank as long as timing is met. External timing for
this signal is not critical and a level shifter can be used.
• DCI cascade can be used to free up the VRN/VRP pins if another bank is available for
the DCI master.
Termination is not required for LPDDR2 memory interfaces. For more information, contact your
TIP:
memory vendor. The termination guidelines can be used in case termination is required.
Internal V is used in this example.
REF
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
www.xilinx.com
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