Xilinx Zynq-7000 User Manual page 54

8. All user-design RTL files and constraints files (XDC files) can be viewed in the Sources >
Libraries tab
X-Ref Target - Figure 1-35
9. The Vivado Design Suite supports Open IP Example Design flow. To create the example
design using this flow right-click the IP in the Source Window, as shown in
and select.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
(Figure 1-35).
Figure 1-35: Vivado Project – RTL and Constraints Files
www.xilinx.com
Figure 1-36
54
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