Xilinx Zynq-7000 User Manual page 127

X-Ref Target - Figure 1-54
The ECC mode is optional and supported only for a 72-bit data width. The data mask feature
is disabled when ECC mode is enabled. When ECC mode is enabled, the entire DQ width is
always written. The DRAM DM bits cannot be used because the ECC operates over the entire
DQ data width. A top-level parameter called ECC controls the addition of ECC logic. When
this parameter is set to "ON," ECC is enabled, and when the parameter is set to "OFF," ECC
is disabled.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-54: ECC Block Diagram
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