Xilinx Zynq-7000 User Manual page 552

Table 4-6: Modules in user_design/rtl/controller Directory (Cont'd)
(1)
Name
rank_common.v
rank_mach.v
round_robin_arb.v
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
arb_mux in generated output is now mig_7series_v4_1_arb_mux.
user_design/rtl/ip_top
This directory contains the user design
Table 4-7: Modules in user_design/rtl/ip_top Directory
(1)
Name
mem_intfc.v
memc_ui_top.v
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
mem_intfc in generated output is now mig_7series_v4_1_mem_intfc.
user_design/rtl/phy
This directory contains the 7 series FPGA memory interface PHY implementation
(Table 4-8).
Table 4-8: Modules in user_design/rtl/phy Directory
(1)
Name
ddr_byte_group_io
ddr_byte_lane
ddr_calib_top
ddr_mc_phy
ddr_mc_phy_wrapper
ddr_of_pre_fifo
ddr_phy_4lanes
ddr_phy_init_lpddr2
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Description
This module contains logic common to all rank machines. It contains a
clock prescaler and arbiters for refresh and periodic read.
This is the top-level rank machine structural block.
This is a simple round-robin arbiter.
(Table 4-7).
Description
This is the top-level memory interface block that instantiates the
controller and the PHY.
This is the top-level Memory Controller module.
Description
This module contains the parameterizable I/O logic instantiations and the
I/O terminations for a single byte lane.
This module contains the primitive instantiations required within an output
or input byte lane.
This is the top-level module for the memory physical layer interface.
This module is a parameterizable wrapper instantiating up to three I/O
banks, each with 4-lane PHY primitives.
This wrapper file encompasses the MC_PHY module instantiation and
handles the vector remapping between the MC_PHY ports and your LPDDR2
ports.
This module extends the depth of a PHASER OUT_FIFO up to four entries.
This module is the parameterizable 4-lane PHY in an I/O bank.
This module contains the memory initialization and overall master state
control during initialization and calibration.
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