Xilinx Zynq-7000 User Manual page 462

Table 3-15: RLDRAM II Memory Interface Solution Pinout Parameters
Parameter Description
0, 1, 2. This parameter varies based
on the pinout and should not be
MASTER_PHY_CTL
changed manually in generated
design.
Three fields, one per possible I/O
bank. Defines the byte lanes being
used in a given I/O bank. A 1 in a bit
BYTE_LANES_B0,
position indicates a byte lane is used,
BYTE_LANES_B1,
and a 0 indicates unused. This
BYTE_LANES_B2
parameter varies based on the pinout
and should not be changed manually
in generated design.
Three fields, one per possible I/O
bank. Defines the byte lanes for a
given I/O bank. A 1 in a bit position
DATA_CTL_B0, indicates a byte lane is used for data,
DATA_CTL_B1, and a 0 indicates it is used for
DATA_CTL_B2 address/control. This parameter
varies based on the pinout and
should not be changed manually in
generated design.
RLDRAM II Only. Three fields, one per
possible I/O bank. Defines which
read capture clocks are used for each
byte lane in given bank. MRCC read
capture clocks are placed in byte
lanes 1 and/or 2, where parameter is
defined for each data byte lane to
indicate which read clock to use for
CPT_CLK_SEL_B0, the capture clock. 8 bits per byte
CPT_CLK_SEL_B1, lane, defined such that:
CPT_CLK_SEL_B2
• [3:0] – 1, 2 to indicate which of two
• [7:4] – 0 (bank below), 1 (current
This parameter varies based on the
pinout and should not be changed
manually in generated design.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
capture clock sources
bank), 2 (bank above) to indicate in
which bank the clock is placed.
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Example
The bank where the master PHY_CONTROL resides
(usually corresponds to MMCM/PLL bank
location).
Ordering of bits from MSB to LSB is T0, T1, T2, and
T3 byte groups.
4'b1101 = Three byte lanes in use for a given
bank, with one not in use.
4'b1100 = Two data byte lanes, and, if used with a
BYTE_LANES_B0 parameter as in the example
shown above, one address/control.
32'h12_12_11_11 = Four data byte lanes, all using
the clocks in the same bank.
32'h21_22_11_11 = Four data byte lanes, two
lanes using the capture clock from the bank above
(16'h21_22), two using the capture clock from the
current bank (16'h11_11).
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