Xilinx Zynq-7000 User Manual page 485

X-Ref Target - Figure 3-64
2. Under the Simulation tab as shown in
as 1 ms (there are simulation RTL directives which stop the simulation after certain
period of time, which is less than 1 ms). Apply the settings and select OK.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Figure 3-64: Simulation with Vivado Simulator
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Figure 3-64, set the xsim.simulate.runtime
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