Xilinx Zynq-7000 User Manual page 672

9. In the breakout region, route signal lines in the middle of the via void aperture. Avoid
routing at the edge of via voids
X-Ref Target - Figure A-4
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Appendix A:
(Figure A-4).
Figure A-4: Breakout Region Routing
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General Memory Routing Guidelines
UG583_c2_15_051915
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