Xilinx Zynq-7000 User Manual page 534

X-Ref Target - Figure 4-22
Bank Selection
This feature allows the selection of bytes for the memory interface. Bytes can be selected
for different classes of memory signals, such as:
• Address and control signals
• Data signals
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Figure 4-22: Pin/Bank Selection Mode
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