Xilinx Zynq-7000 User Manual page 51

4. After generating the MIG core design, the project window appears as shown in
Figure 1-31.
X-Ref Target - Figure 1-31
Figure 1-31: Vivado Tool Project Window (After IP Generation)
5. After project creation, the XCI file is added to the Project Hierarchy. The same view also
displays the module hierarchies of the user design. The list of HDL and XDC files is
available in the IP Sources view in the Sources window. Double-clicking on any module
or file opens the file in the Vivado Editor. These files are read only.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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