Xilinx Zynq-7000 User Manual page 306

8. All user-design RTL and constraints files (XDC files) can be viewed in the Sources >
Libraries tab
X-Ref Target - Figure 2-34
9. The Vivado Design Suite supports the Open IP Example Design flow. To create the
example design using this flow, right-click the IP in the Source Window, as shown in
Figure 2-35
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
(Figure 2-34).
Figure 2-34: Vivado Project – RTL and Constraints Files
and select.
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Chapter 2: QDR II+ Memory Interface Solution
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