Implementation Details - Xilinx Zynq-7000 User Manual

X-Ref Target - Figure 3-52
Simulation
Reset
Memory Initialization
Write
0-F-0-F-0-F-F-0
Read
0-F-0-F-0-F-F-0
Write
A-5-0-F
or
A-5-0-F-9-6-D-2
Read
A-5-0-F
or
A-5-0-F-9-6-D-2
Write
A-5-0-F-3-C-3-C
or
A-5-0-F-9-6-D-2
Read
A-5-0-F
or
A-5-0-F-9-6-D-2
Calibration of Read Clock and Data
PHASER_IN clocks all ISERDES used to capture read data (DQ) associated with the
corresponding byte group. ICLKDIV is also the write clock for the read data IN_FIFOs. One
PHASER_IN block is associated with a group of 12 I/Os. Each I/O bank in the FPGA has four
PHASER_IN blocks, and hence four read data bytes can be placed in a bank.

Implementation Details

This stage of read leveling is performed one byte at a time, where the read clock is
center-aligned to the corresponding read data in that byte group. At the start of this stage,
a single write command is issued to address location 0 in each bank of the memory device
(eight banks for RLDRAM II and 16 for RLDRAM 3). All banks are used to ensure no matter
which burst length is selected, the read commands can be issued to ensure read data is
returned back-to-back without any gaps in the data stream.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
RLDRAM II
Reset
Memory Initialization
Write
Recalibrate read path
0-F-0-F-0-F-F-0
at each write
adjustment
Read
0-F-0-F-0-F-F-0
Write
A-5-0-F
Read
A-5-0-F
Write Cal
Adjust
Done?
Write Path
Write
A-5-0-F-3-C-3-C
Read
A-5-0-F
Figure 3-52: Calibration Flow Diagram
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RLDRAM III
Reset
Memory Initialization
Read
Writes not needed to
F-0-F-0-F-0-F-0
calibrate read path
Turn Off Read Training
Register
Write
A-5-0-F-9-6-D-2
Read
A-5-0-F-9-6-D-2
Write Cal
Adjust
Done?
Write Path
Write
0-F-0-F-0-F-F-0
Different pattern
from RTR
Read
0-F-0-F-0-F-F-0
Write
A-5-0-F-9-6-D-2
Read
A-5-0-F-9-6-D-2
Write
A-5-0-F-9-6-D-2
Read
A-5-0-F-9-6-D-2
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