Xilinx Zynq-7000 User Manual page 106

UE_EN_IRQ are set to 1 (enabled), the value of the Interrupt signal is the logical OR between
the CE_STATUS and UE_STATUS bits.
Table 1-25: ECC Interrupt Enable Register Bit Definitions
Core
Bits Name
Access
31:2 Reserved RSVD
1 CE_EN_IRQ R/W
0 UE_EN_IRQ R/W
ECC_ON_OFF
The ECC On/Off Control Register allows the application to enable or disable ECC checking.
The design parameter, C_ECC_ONOFF_RESET_VALUE (default on) determines the reset value
for the enable/disable setting of ECC. This facilitates start-up operations when ECC might or
might not be initialized in the external memory. When disabled, ECC checking is disabled
for read but ECC generation is active for write operations.
Table 1-26: ECC On/Off Control Register Bit Definitions
Core
Bits Name
Access
31:1 Reserved RSVD
0 ECC_ON_OFF R/W
CE_CNT
This register counts the number of occurrences of correctable errors. It can be cleared or
preset to any value using a register write. When the counter reaches its maximum value, it
does not wrap around, but instead it stops incrementing and remains at the maximum
value. The width of the counter is defined by the value of the C_CE_COUNTER_WIDTH
parameter. The value of the CE counter width is fixed to eight bits.
Table 1-27: Correctable Error Counter Register Bit Definitions
Bits Name Core Access Reset Value Description
31:8 Reserved RSVD
7:0 CE_CNT R/W
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Reset
Description
Value
– Reserved
If 1, the value of the CE_STATUS bit of ECC Status register is
propagated to the Interrupt signal. If 0, the value of the
0
CE_STATUS bit of ECC Status Register is not propagated to the
Interrupt signal.
If 1, the value of the UE_STATUS bit of ECC Status register is
propagated to the Interrupt signal. If 0, the value of the
0
UE_STATUS bit of ECC Status Register is not propagated to the
Interrupt signal.
Reset Value Description
– Reserved
Specified by If 0, ECC checking is disabled on read operations. (ECC
design generation is enabled on write operations when C_ECC = 1).
parameter, If 1, ECC checking is enabled on read operations. All
C_ECC_ONOFF_ correctable and uncorrectable error conditions are captured
RESET_VALUE and status is updated.
– Reserved
0 Holds the number of correctable errors encountered.
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