Xilinx Zynq-7000 User Manual page 553

Table 4-8: Modules in user_design/rtl/phy Directory (Cont'd)
(1)
Name
ddr_phy_rdlvl
ddr_phy_top
ddr_phy_wrlvl_off_delay.v This module sets up the command and write datapath delays.
ddr_bitslip.v
ddr_phy_pd.v
ddr_phy_pd_top.v
ddr_phy_prbs_rdlvl.v
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
ddr_byte_group_io in generated output is now mig_7series_v4_1_ddr_byte_group_io.
user_design/rtl/ui
This directory contains the user interface code that mediates between the native interface
of the Memory Controller and user applications
Table 4-9: Modules In user_design/rtl/ui Directory
(1)
Name
ui_cmd.v
ui_rd_data.v
ui_wr_data.v
ui_top.v
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
ui_cmd in generated output is now mig_7series_v4_1_ui_cmd.
<component name>/user_design/xdc
Table 4-10 lists the modules in the user_design/xdc directory.
Table 4-10: Modules in user_design/xdc Directory
Name
<component_name>.xdc
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Description
This module contains the Read leveling Stage1 calibration logic.
This is the top-level module for the physical layer.
This module contains the shift registers and MUXes to compensate the
bitslip and align the read data.
This module contains the Phase detector logic to compensate any drift over
the voltage and temperature variations.
This module is the top instance of phy_pd. This is used to instantiate Phase
detector based on different calibration mode of parallel or sequential
detection.
This module contains calibration logic to perform data valid window
detection and capture clock alignment using PRBS data pattern.
Description
This is the user interface command port.
This is the user interface read buffer. It reorders read data returned from the
Memory Controller back to the request order.
This is the user interface write buffer.
This is the top-level of the Memory Controller user interface.
Description
This is the XDC for the core and the user design.
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(Table 4-9).
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