Xilinx Zynq-7000 User Manual page 83

Simulation Flow Using Vivado Simulator
1. In the Open IP Example Design Vivado project, under Flow Navigator, select
Simulation Settings
X-Ref Target - Figure 1-46
2. Under the Simulation tab as shown in
as 1 ms (there are simulation RTL directives which stop the simulation after a certain
period of time, which is less than 1 ms). Apply the settings and select OK.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
(Figure 1-46).
Figure 1-46: Simulation with Vivado Simulator
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Figure 1-46, set the xsim.simulate.runtime
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