Xilinx Zynq-7000 User Manual page 191

Table 1-66: DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters (Cont'd)
Parameter
ODT_MAP
CS_MAP
PARITY_MAP
RAS_MAP
WE_MAP
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Bank and byte lane
position information for
the ODT. This parameter
is referred to as one of
the Address/Control byte
groups. See
ADDR_MAP
description. This
parameter varies based
on the pinout and should
not be changed manually
in generated design.
Bank and byte lane
position information for
the chip select. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
Bank and byte lane
position information for
the parity bit. Parity bit
exists for RDIMMs only.
See the ADDR_MAP
description. This
parameter varies based on
the pinout and should not
be changed manually in
generated design.
Bank and byte lane
position information for
the RAS command. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
Bank and byte lane
position information for
the WE command. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
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Example
See the ADDR_MAP example.
See the ADDR_MAP example.
See the ADDR_MAP example.
See the ADDR_MAP example.
See the ADDR_MAP example.
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