Xilinx Zynq-7000 User Manual page 622

Table 4-25: 7 Series FPGA Memory Solution Configuration Parameters
Parameter
(1)
REFCLK_FREQ
(2)
SIM_BYPASS_INIT_CAL
nCK_PER_CLK
nCS_PER_RANK
DQS_CNT_WIDTH
ADDR_WIDTH
BANK_WIDTH
CS_WIDTH
CK_WIDTH
CKE_WIDTH
COL_WIDTH
RANK_WIDTH
ROW_WIDTH
DM_WIDTH
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Description
This is the reference clock frequency for
IDELAYCTRLs. This can be set to 200.0 for any
speed grade device. For more information, see
the IDELAYE2 (IDELAY) and ODELAYE2
(ODELAY) Attribute Summary table in the
7 Series FPGAs SelectIO™ Resources User
Guide
[Ref 2]. This parameter should not be
changed.
This is the calibration procedure for simulation.
"OFF" is not supported in simulation. "OFF"
must be used for hardware implementations.
"FAST" enables a fast version of read and write
leveling. "SIM_FULL" enables full calibration
but skips the power-up initialization delay.
"SIM_INIT_CAL_FULL" enables full calibration
including the power-up delays.
This is the number of memory clocks per clock.
This parameter should not be changed.
This is the number of unique CS outputs per
rank for the PHY.
This is the number of bits required to index the
DQS bus and is given by
ceil(log (DQS_WIDTH)).
2
This is the memory address bus width. It is
equal to RANK_WIDTH + BANK_WIDTH +
ROW_WIDTH + COL_WIDTH.
This is the number of memory bank address
bits.
This is the number of unique CS outputs to
memory.
This is the number of CK/CK# outputs to
memory.
This is the number of CKE outputs to memory.
This is the number of memory column address
bits.
This is the number of bits required to index the
RANK bus.
This is the DRAM component address bus
width.
This is the number of data mask bits.
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Options
200.0
"OFF"
"FAST"
"SIM_FULL"
2
1, 2
This option is based on the selected
memory device.
This option is based on the selected
MIG tool configuration.
This option is based on the selected
MIG tool configuration.
This option is based on the selected
MIG tool configuration.
This option is based on the selected
memory device.
This parameter value is 1 for both
Single and Dual rank devices.
This option is based on the selected
memory device.
DQ_WIDTH/8
622
Send Feedback