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Xilinx Zynq-7000 User Manual

Memory interface solutions

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Zynq-7000 AP SoC and

7 Series Devices

Memory Interface

Solutions v4.1

User Guide

UG586 November 30, 2016

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Page 1 Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.1 User Guide UG586 November 30, 2016...
Page 2 • Updated sys_rst descriptions in DDR3 and DD2 Configuration sections. • Added note in Debug Signals section. • Updated reset description in General Checks section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 3 • Added Clocking sections to QDR II+, RLDRAM II/RLDRAM 3, and LPDDR2 chapters. 06/24/2015 RLDRAM II/ RLDRAM 3 • Added address/control signal and SSI descriptions in Pinout Requirements section. • Updated Input Clock Guidelines section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 4 Chapter 4 Continued • Corrected app_wdf_data[APP_DATA_WIDTH – 1:0] and app_wdf_mask[APP_MASK_WIDTH – 1:0] sections. • Updated Fig. 4-43: Clocking Architecture. • Updated Read Path section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 5 • Updated Figs. 4-57 to 4-59 and Figs. 4-62 to 4-63. • Updated 2:1 description in Write Path section. • Updated rules in Termination section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 6 Continued the example_top Module. • Updated package length descriptions in Trace Length Requirements section. • Added simulation description in Note in Read Path section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 7 • Added new code constraints in Configuration section. • Updated Table 4-4: Files in example_design/sim Directory. • Updated file description in Simulation Flow Using IES and VCS Script Files section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 8 • Added OOC description in Customizing the Core section. • Added simulator flows. • Added note on read latency in Debug section. Chapter 5 • Added Out of Context content. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 9 • Added #4 note to Table 4-25 7 Series FPGA Memory Solution Configuration Parameters. • Updated description in app_wdf_mask[APP_MASK_WIDTH - 1:0] section. • Added Memory Address Mapping description in User Interface section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 10 • Updated descriptions in Manual Pinout Changes section. • Added new calibration description in Calibration section. • Updated Table 3-26 Physical Layer Simple Status Bus Description Defined in the rld_phy_top Module. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 11 • Added description in Verifying the Simulation Using the Example Design section. • Reworked Design Guidelines DDR3 SDRAM section. • Added new debug section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 12 • Added description in Verifying the Simulation Using the Example Design section. Chapter 4 • Added new LPDDR2 SDRAM section. Chapter 6 • Updated to new GUIs. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 13 • Added descriptions in RLDRAM II. • Added RLDRAM II description in Configuration. • Added description to Verifying the Simulation Using the Example Design. • Added Debug section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 14 • Chapter 6: Added new chapter on migrating to Vivado Design Suite. Revised the recommended total electrical delay on CK/CK# relative to DQS/DQS# on 06/13/2012 page 191. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 15 • Chapter 3: Removed Input Clock Period option from Controller Options. Added Input Clock Period option to Memory Options. Added Reference Clock option to FPGA Options. Added Debugging RLDRAM II and RLDRAM 3 Designs. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 16 CLKFBOUT_MULT, CLKOUT0_DIVIDE, CLKOUT1_DIVIDE, CLKOUT2_DIVIDE, and CLKOUT3_DIVIDE. Updated Table 3-15. Added paragraph about DCI and IN_TERM after Table 3-24. • Added Chapter 5, Multicontroller Design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 17 Pin/Bank selection mode on page 285. Added Internal Termination for High Range Banks option under Figure 2-22. Updated Implementation Details, page 324. • Chapter 3: Added new chapter on RLDRAM II. 03/01/2011 Initial Xilinx release. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 18 Core Architecture..............575 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1...
Page 19 Xilinx Resources ........
Page 20: Introduction
192). • Controller and user interface operate at 1/4 the memory clock frequency. For a full list of supported features, see the Zynq-7000 AP SoC and 7 Series FPGAs Memory Interface Solutions Data Sheet (DS176) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1...
Page 21: Using Mig In The Vivado Design Suite
2. To create a new project, click the Create New Project option shown in Figure 1-1 open the page as shown in Figure 1-2. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 22 Project Location. Based on the details provided, the project is saved in the directory. X-Ref Target - Figure 1-3 Figure 1-3: Project Name Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 23 If the project was not created earlier, proceed to the next page. X-Ref Target - Figure 1-5 Figure 1-5: Add Sources Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 24 1-7). If the constraints file exists in the repository, it can be added to the project. Proceed to the next page if the constraints file does not exist. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 25 The Default Part page appears as shown in Figure 1-8. X-Ref Target - Figure 1-8 Figure 1-8: Default Part (Default Window) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 26 Figure 1-9: Default Part (Customized Window) Apart from selecting the parts by using Parts option, parts can be selected by choosing the Boards option, which brings up the evaluation boards supported by Xilinx (Figure 1-10). With this option, design can be targeted for the various evaluation boards.
Page 27 1-11). This includes the summary of selected project details. X-Ref Target - Figure 1-11 Figure 1-11: New Project Summary 10. Click Finish to complete the project creation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 28 1-12) or you can search from the Search tool bar for the string “MIG.” X-Ref Target - Figure 1-12 Figure 1-12: IP Catalog Window – Memory Interface Generator Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 29 “Verilog” in the Vivado Design Suite before invoking the MIG tool. If the AXI4 interface is not selected, the user interface (UI) is the primary interface. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 30 This name should always start with an alphabetical character and can end with an alphanumeric character. When invoked from Xilinx Platform Studio (XPS), the component name is corrected to be the IP instance name from XPS. 4. Click Next to display the Pin Compatible FPGAs page.
Page 31 Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution Xilinx 7 series devices using stacked silicon interconnect (SSI) technology have super logic regions (SLRs). Memory interfaces cannot span across SLRs. If the device selected or a compatible device that is selected has SLRs, the MIG tool ensures that the interface does not cross SLR boundaries.
Page 32 2. Click Next to display the Controller Options page (Figure 1-16). X-Ref Target - Figure 1-16 UG586_c1_11_120311 Figure 1-16: Memory Type and Controller Selection Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 33 This page is partitioned into a maximum of nine sections. The number of partitions depends on the type of memory selected. The controller options page also contains these pull-down menus to modify different features of the design: Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 34 Data Mask – This option allocates data mask pins when selected. This should be deselected to deallocate data mask pins and increase pin efficiency. Also, this is disabled for memory parts that do not support data mask. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 35 To create a custom part, click the Create Custom Part below the Memory Part pull-down menu. A new page appears, as shown in Figure 1-19. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 36 8. Click Next to display the Memory Options page (or the AXI Parameter Options page if AXI Enable is checked on the Memory Type selection page). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 37 AXI masters. • Arbitration Scheme – Selects the arbitration scheme between read and write address channels. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 38 Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution X-Ref Target - Figure 1-20 UG586_c1_22_090511 Figure 1-20: Setting AXI Parameter Options Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 39 The DDR2 SDRAM interface has a separate option to select the number of memory clocks called Memory Clock Selection. Each component has a Number of Memory Clocks setting, and the maximum number of clocks allowed is four. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 40 Click Next to display the FPGA Options page. FPGA Options Figure 1-22 shows the FPGA Options page. X-Ref Target - Figure 1-22 Figure 1-22: FPGA Options Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 41 V pins for normal I/O usage. Internal V should only be used for data rates of 800 Mb/s or below. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 42 Internal Termination for High Range Banks – The internal termination option can be set to 40, 50, or 60Ω or disabled. This selection is only for High Range banks. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 43 You cannot proceed until the MIG DRC has been validated by clicking Validate. X-Ref Target - Figure 1-24 Figure 1-24: Pin/Bank Selection Mode Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 44 VCCAUX_IO is common to all banks in these groups. The memory interface must have the same VCCAUX_IO for all banks used in the interface. The MIG core automatically sets the VCCAUX_IO constraint appropriately for the data rate requested. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 45 SSTL15. If sys_clk is not connected in a memory interface bank, the MIG tool selects an appropriate standard such as LVCMOS18 or LVDS. The XDC can be modified as desired after generation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 46 This page provides the complete details about the 7 series FPGA memory core selection, interface parameters, IP catalog options, and FPGA options of the active project (Figure 1-27). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 47 License Agreement box to accept it. If the license agreement is not agreed to, the memory model is not made available. A memory model is necessary to simulate the design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 48 Click Generate to generate the design files. The MIG tool generates two output directories: example_design and user_design. After generating the design, the MIG GUI closes. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 49 1. After clicking Generate, the Generate Output Products window appears. This window has the Out-of-Context Settings as shown in Figure 1-29. X-Ref Target - Figure 1-29 Figure 1-29: Generate Output Products Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 50 3. MIG core designs comply with “Hierarchical Design" flow in Vivado. For more information, see the Vivado Design Suite User Guide: Hierarchical Design (UG905) [Ref 5] and the Vivado Design Suite Tutorial: Hierarchical Design (UG946) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 51 IP Sources view in the Sources window. Double-clicking on any module or file opens the file in the Vivado Editor. These files are read only. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 52 6. All MIG generated user design RTL and XDC files are automatically added to the project. If files are modified and you wish to regenerate them, right-click the XCI file and select Generate Output Products (Figure 1-33). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 53 7. Clicking the Generate Output Products option brings up the Manage Outputs window (Figure 1-34). X-Ref Target - Figure 1-34 Figure 1-34: Generate Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 54 9. The Vivado Design Suite supports Open IP Example Design flow. To create the example design using this flow right-click the IP in the Source Window, as shown in Figure 1-36 and select. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 55 This launches a new Vivado project with all example design files and a copy of the IP. This project has example_top as the Implementation top directory, and sim_tb_top as the Simulation top directory, as shown in Figure 1-37. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 56 Right-click the XCI file and click Recustomize IP (Figure 1-38) to open the MIG GUI and regenerate the design with the preferred options. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 57 The output directory structure of the selected Memory Controller (MC) design from the MIG tool is shown here. In the <component name> directory, three folders are created: • docs • example_design • user_design Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 58 Table 1-1: Files in example_design/rtl Directory Name Description This top-level module serves as an example for connecting the user example_top.v/vhd design to the 7 series FPGAs memory interface core. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 59 Table 1-3: Files in example_design/par Directory Name Description example_top.xdc This is the XDC for the core and the example design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 60 <component_name>_mig_sim.v/vhd is used in simulations. The top-level wrapper file serves as an example for connecting the user_design to the MIG core. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 61 This module contains logic common to all rank machines. It contains a rank_common.v clock prescaler and arbiters for refresh and periodic read. rank_mach.v This is the top-level rank machine structural block. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 62 This module contains the logic to provide the required delay on the ddr_phy_ck_addr_cmd_delay address and control signals. ddr_phy_dqs_delay This module contains the DQS to DQ phase offset logic. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 63 Table 1-10: Files in user_design/xdc Directory Name Description <component_name>.xdc This is the XDC for the core and the user design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 64 Pins related to one strobe set should reside in the same byte group. ° The strobe pair (DQS) should be allocated to the DQS I/O pair. ° Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 65 Quick Start Example Design Overview After the core is successfully generated, the example design HDL can be processed through the Xilinx implementation toolset. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 66 Figure 1-39: Synthesizable Example Design Block Diagram Figure 1-40 shows the simulation result of a simple read and write transaction between the tb_top and memc_intfc modules. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 67 (R/W, R, W) and addresses are determined by PRBS generator logic in the traffic generator module. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 68 This parameter defines the end boundary Sets the memory end address for the port address space. The END_ADDRESS boundary. least-significant Bits[3:0] of this value are ignored. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 69 • CGEN_ALL (default): This option turns on all of the options above and allows addr_mode_i, instr_mode_i, and bl_mode_i to select the type of generation during run time. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 70 Select a victim DQ line whose state 0 to NUM_DQ_PINS. SEL_VICTIM_LINE is always at logic High. When value = NUM_DQ_PINS, all DQ pins have the same Hammer pattern. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 71 4: DGEN_NEIGHBOR. All 1s are on the DQ pins during the rising edge of DQS except one pin. The address determines the exception pin location. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 72 0x2000 0x4FFF 0x00002000 0xFFFF8000 0x2000 0x5FFF 0x00002000 0xFFFF8000 0x2000 0x6FFF 0x00002000 0xFFFF8000 0x2000 0x7FFF 0x00002000 0xFFFF8000 0x2000 0x8FFF 0x00002000 0xFFFF0000 0x2000 0x9FFF 0x00002000 0xFFFF0000 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 73 Low. This signal is only used to send write commands to the QDR II+ qdr_wr_cmd_o Output user interface. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 74 • 0x3: SEQUENTIAL address mode. The address is generated from the internal address counter. The increment is determined by the user interface port width. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 75 Input User-defined simple data 2 for simple 8 repeat data pattern. simple_data3[31:0] Input User-defined simple data 3 for simple 8 repeat data pattern. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 76 (by default, the addr_mode_i, instr_mode_i, and bl_mode_i inputs are set to select PRBS mode). Traffic Test Flow 1. The addr_mode_i input is set to the desired mode (PRBS is the default). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 77 The details of the clocks in Figure 1-41 are provided in Clocking Architecture, page 119. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 78 This follows the standard AXI4 protocol. X-Ref Target - Figure 1-42 Figure 1-42: AXI4 Interface Write Cycle Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 79 This signal is asserted for one clock indicating that the current read transaction is read_cmptd completed. When asserted, this signal indicates that the read transaction to the memory resulted read_err in an error. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 80 • 3'b001: Data write transaction • 3'b010: Waiting for acknowledgment for written data • 3'b011: Dummy data write transaction • 3'b100: Waiting for response from the response channel Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 81 AXI wrapper read FSM state when timeout (watchdog timer should be enabled) occurs: • 2'b01: Read command transaction • 2'b10: Data read transaction Incorrect response ID presented by the AXI slave Read error response on AXI Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 82 The AXI4 write and read transactions are started only after the init_calib_complete signal is asserted. Setting Up for Simulation The Xilinx UNISIM library must be mapped into the simulator. IMPORTANT: The test bench provided with the example design supports these pre-implementation simulations: •...
Page 83 1 ms (there are simulation RTL directives which stop the simulation after a certain period of time, which is less than 1 ms). Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 84 RTL directives which stop the simulation after certain period of time, which is less than 1 ms), set modelsim.simulate.vsim.more_options to -novopt as shown in Figure 1-46. 3. Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 85 1. In the Open IP Example Design Vivado project, under Flow Navigator select Simulation Settings. 2. Select Target simulator as Verilog Compiler Simulator (VCS). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 86 Figure 1-49: Simulation with VCS 4. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulation as shown in Figure 1-47. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 87 Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there are simulation RTL directives which stop the simulation after certain period of time which is less than 1 ms) as shown in Figure 1-50. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 88 5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 89: Synplify Pro Black Box Testing
Design Source. For example: <project_dir>/<Component_Name>_example/ <Component_Name>_example.srcs/sources_1/ip/<Component_Name>/<Component_Name>.dcp 9. Add the .xdc file generated in step 2 to the Vivado project as a constraint file. For example: <project_dir>/<Component_Name>_example/ <Component_Name>_example.srcs/constrs_1/imports/par/example_top.xdc Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 90: Core Architecture
1. System clock (sys_clk_p and sys_clk_n/sys_clk_i), Reference clock (clk_ref_p and clk_ref_n/clk_ref_i), and system reset (sys_rst_n) port connections are not shown in block diagram. Figure 1-51: 7 Series FPGAs Memory Interface Solution Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 91 400 MHz depending on memory interface frequency and speed grade of the FPGA. Based on the IODELAY_GROUP attribute that is set, the Vivado Design Suite replicates the IDELAYCTRLs for each region where the IDELAY blocks exist. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 92 In the example design, this signal is always tied to 1. app_sr_req Input This input is reserved and should be tied to 0. app_sr_active Output This output is reserved. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 93 This input specifies the command for the request currently being submitted to the UI. The available commands are shown in Table 1-18. Table 1-18: Commands for app_cmd[2:0] Operation app_cmd[2:0] Code Read Write Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 94 All the bank machines are occupied (can be viewed as the command buffer being ° full) A read is requested and the read buffer is full Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 95 When asserted, this active-High input acknowledges a ZQ calibration request and indicates that the command has been sent from the Memory Controller to the PHY. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 96 If ECC is enabled, all write commands with any of the mask bits enabled are issued as read-modify-write operation. If ECC is enabled, all write commands with none of the mask bits enabled are issued as write operation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 97 Additionally, the base/high address pair must be aligned to a multiple of the accessible size. The minimum accessible size is 4,096 bytes. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 98 Protection type. (Not used in the s_axi_awprot Input current implementation.) Write address valid. This signal s_axi_awvalid Input High indicates that valid write address and control information are available. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 99 Read ID tag. s_axi_rdata C_AXI_DATA_WIDTH Output Read data. s_axi_rresp Output Read response. s_axi_rlast Output Read last. s_axi_rvalid Output Read valid. s_axi_rready Input Read ready. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 100 The read address channel is always given priority in this mode. The requests from the write address channel are processed when there are no pending requests from the read address channel or the starve limit for read is reached. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 101 The ecc_single signal indicates if there has been a correctable error, and the ecc_multiple signal indicates if there has been an uncorrectable error. The widths of ecc_multiple and ecc_single are based on the C_NCK_PER_CLK parameter. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 102 During operation, after the error has been inserted into the datapath, the register clears itself. AXI4-Lite Slave Control/Status Register Interface Parameters Table 1-21 lists the AXI4-Lite slave interface parameters. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 103 C_S_AXI_CTRL_ADDR_WIDTH Input Read address. s_axi_ctrl_arvalid Input High Read address valid. s_axi_ctrl_arready Output High Read address. s_axi_ctrl_rdata C_S_AXI_CTRL_DATA_WIDTH Output Read data. s_axi_ctrl_rvalid Output Read valid. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 104 Uncorrectable Error First Failing Data Register UE_FFD 0x20C Uncorrectable Error First Failing Data Register [127:96] (0x210–0x27C) Reserved 0x280 UE_FFE Uncorrectable Error First Failing ECC Register (0x284–0x2BC) Reserved Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 105 This register determines if the values of the CE_STATUS and UE_STATUS bits in the ECC Status Register assert the Interrupt output signal (ECC_Interrupt). If both CE_EN_IRQ and Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 106 Table 1-27: Correctable Error Counter Register Bit Definitions Bits Name Core Access Reset Value Description 31:8 Reserved RSVD – Reserved CE_CNT Holds the number of correctable errors encountered. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 107 This register stores the (corrected) failing data (Bits[63:32]) of the first occurrence of an access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 108 When the CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the ECC of the next correctable error. Storing of the failing ECC is enabled after reset. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 109 Table 1-37: Uncorrectable Error First Failing Address [31:0] Register Bit Definitions Bits Name Core Access Reset Value Description Address (Bits[63:32]) of the first occurrence of an 31:0 UE_FFA[63:32] uncorrectable error Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 110 Table 1-40: Uncorrectable Error First Failing Data [95:64] Register Bit Definitions Bits Name Core Access Reset Value Description Data (Bits[95:64]) of the first occurrence of an 31:0 UE_FFD[95:64] uncorrectable error. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 111 (word 0 or Bits[31:0]) of the subsequent data written to the memory without affecting the ECC bits written. After the fault has been injected, the Fault Injection Data register is cleared automatically. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 112 This register is only implemented if C_ECC_TEST = “ON” or ECC_TEST_FI_XOR = “ON” and ECC = “ON” in a MIG design in the Vivado IP catalog. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 113 Injecting faults should be performed in a critical region in software; that is, writing this register and the subsequent write to memory must not be interrupted. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 114 Input This input selects the bank for the current request. bank_mach_next[] Output This output is reserved and should be left unconnected. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 115 For read commands, data_buf_addr is an address in the buffer that Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 116 When asserted, this signal indicates that the core is reading data from the user design for a write command. This signal can be tied to the chip select of a buffer in the user design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 117 This bus can be combined with rd_data_addr and applied to the address input of a buffer in the user design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 118 When asserted, this active-High input acknowledges a ZQ calibration request and indicates that the command has been sent from the Memory Controller to the PHY. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 119 For Low Voltage devices when HP banks are selected for memory interface pins in GUI and the memory frequencies are between 200–400 MHz (excluding 400 MHz), the phase is 0°. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 120 DDR2 or DDR3 SDRAM clock frequency, which depends on 4:1 or 2:1 mode selected in the MIG tool. This PLL also outputs the high-speed DDR2 or DDR3 memory clock. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 121 If a PLL clock drives the IDELAYCTRL input clock, the PLL lock signal needs to be incorporated in the rst_tmp_idelay signal inside the IODELAY_CTRL.v module. This ensures that the clock is stable before being used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 122 The Memory Controller block is organized as four main pieces: • A configurable number of “bank machines” • A configurable number of “rank machines” • A column machine • An arbitration block Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 123 A bank machine precharges a DRAM bank as soon as possible unless another pending request targets the same bank. This is discussed in greater detail in the Precharge Policy section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 124 Arbitration is necessary because several bank machines might request to send row commands (activate and precharge) at the same time. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 125 "Global" in the Generate Output Products settings. After generating the design, the design top-level RTL file should be edited and the ORDERING parameter should be changed to "RELAXED." Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 126 Errors of more than two bits might or might not be detected. Figure 1-54 shows the ECC block diagram. These blocks are instantiated in the Memory Controller (mc.v) module. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 127 DQ data width. A top-level parameter called ECC controls the addition of ECC logic. When this parameter is set to “ON,” ECC is enabled, and when the parameter is set to “OFF,” ECC is disabled. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 128 ECC enabled designs. Table 1-55 shows the available commands when ECC mode is enabled. Table 1-55: Commands for app_cmd[2:0] Operation app_cmd[2:0] Code Write Read Write Bytes Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 129 UI. This signal is four bits wide in 2:1 mode. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 130 ECC decode correct logic can be tested by asserting app_correct_en_i and writing the desired raw pattern as described above. When the data is read back, the operation of decode correct can be observed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 131 I/O bank. A single PHY control block communicates with all four PHASER_IN and PHASER_OUT blocks within the I/O bank. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 132 4 or divided by 2 version of the DDR2 or DDR3 memory clock. A block diagram of the PHY design is shown in Figure 1-56. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 133 Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution X-Ref Target - Figure 1-56 Figure 1-56: PHY Block Diagram Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 134 X-Ref Target - Figure 1-57 Figure 1-57: PHY Overall Initialization and Calibration Sequence Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 135 I/O bank implementation. For two bank implementations, either PHY control block can be designated the master. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 136 Non-Data (ND – 0x04) – This command instructs the PHY control block to read the ° address and command OUT_FIFOs and transfer the data read from those FIFOs to their associated IOIs. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 137 ° 10: Precharge ° 11: Precharge/Activate ° The MIG IP core does not use these internal counters; therefore, this field should be all zeros. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 138 This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles WR_DURATION_3 Vector[5:0] the auxiliary output remains active for a write command. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 139 The PHY control block assumes that valid data associated with a write command is already available in the DQ OUT_FIFO when it is required to be read out. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 140 PHY control block because the default in the dedicated PHY for address/commands can be set to 0 or 1 as needed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 141 Figure 1-58: Address/Command Path Block Diagram The timing diagram of the address/command path from the output of the OUT_FIFO to the FPGA pins is shown in Figure 1-59. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 142 FPGA logic to operate at low frequencies up to 1/4 the frequency of the DDR2 or DDR3 SDRAM clock. Figure 1-60 shows the block diagram of the datapath. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 143 DQ bit from the calibration logic or Memory Controller and writes the data into the storage array in the PHY_Clk clock domain, which is 1/4 the frequency of the DDR2 or DDR3 SDRAM clock. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 144 (BL), BURST_TYPE, CAS latency (CL), CAS write latency (CWL), write recovery for auto precharge (tWR), on-die termination resistor values (RTT_NOM and RTT_WR), and output driver strength (OUTPUT_DRV). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 145 CK/Address/Command/Control byte lanes is set to the center of the passing window. If no failing edges are found the final tap is set to 32. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 146 PHASER_OUT fine and coarse delay adjustment in the 7 series FPGAs. Figure 1-62 shows the write leveling block diagram. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 147 Figure 1-63: Write Leveling Timing Diagram Figure 1-64 shows that the worst-case delay required during write leveling can be one tCK (DDR3 SDRAM clock period). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 148 3. The write_calib_n signal is deasserted when write leveling is performed on all DQSs in all ranks. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 149 MPR pattern on the entire byte. • Minimum data window (MIN_EYE_SIZE) must be met for two edges to be found. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 150 – If asserted, this indicates that the right-edge of the fall window was detected and it validates oneeighty2fuzz as the tap value of the right-edge of the fall window. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 151 Center Equation Rise Window (90 to 180 Case 1 Found Found Found (fuzz2zero + zero2fuzz)/2 Found Case 2 Found Found (fuzz2zero + zero2fuzz)/2 Found Found Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 152 Figure 1-67 shows several different scenarios based on the initial phase relationship between DQS and CK for a UDIMM or RDIMM interface. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 153 If the total delay required is over one clock cycle, the div_cycle_delay input to the PHASER_OUT block need not be asserted because a circular buffer was added to the PHASER_OUT block. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 154 PHASER_IN stage 2 fine delay line to center the capture clock in the valid DQ window. The capture clock is the free-running FREQ_REF clock that is phase aligned to read DQS in the PHASER_IN phase locked stage. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 155 The PHASER_IN fine delay line has 64 taps (A bit time worth of taps. Tap resolution therefore changes with frequency.). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 156 DQS center alignment in the data valid window. X-Ref Target - Figure 1-71 Figure 1-71: Read Leveling Stage 1 Timing Diagram Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 157 All of the dynamic adjustment is hard logic. However, the periodic reads sent to look at DQS is soft logic controlled by the MIG 7 series DDR2/DDR3 controller. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 158 Averaging should be set to 16, but 64 or 256 is acceptable if already set for other XADC channels. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 159 This signal is the same frequency as mem_refclk between 400 MHz to freq_refclk Input – 933 MHz, and 1/2 or 1/4 of mem_refclk for frequencies below 400 MHz. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 160 RTT_NOM and mc_odt [1:0] Input – RTT_WR values. This signal is valid when the CKE_ODT_AUX parameter is set to FALSE. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 161 High CKE assertion for four-rank interfaces. This is the rank accessed by the command mc_rank_cnt [1:0] Input – sequence in the PHY control word. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 162: Designing With The Core
Only supported modifications should be made to the configuration of the core. See Customizing the Core, page 180 for supported configuration parameters. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 163: Interfacing To The Core
PHY to MC Clock Memory Interface AXI Byte Address [7:0] (LSBs) UI Data Width Ratio Data Width Masking A[7:0] A[7:1], 1’b0 A[7:2], 2’b00 A[7:3], 3’b000 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 164 These addressing schemes are shown in Figure 1-72 Figure 1-73. X-Ref Target - Figure 1-72 Figure 1-72: Memory Address Mapping for Bank-Row-Column Mode in UI Module Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 165 COLUMN Address Bits Bits R14 R13 R12 R11 R10 R9 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Remapped Address with TG_TEST Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 166 Figure 1-74. X-Ref Target - Figure 1-74 Figure 1-74: UI Command Timing Diagram with app_rdy Asserted Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 167 Note 3, the maximum delay is two clock cycles. X-Ref Target - Figure 1-75 Figure 1-75: 4:1 Mode UI Interface Write Timing Diagram (Memory Burst Type = BL8) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 168 64-bit data driven is 0000_0806_0000_0805 (Hex), the data at the DRAM interface is as shown in Figure 1-78. This is for a Burst Length 8 (BL8) transaction. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 169 Figure 1-80 shows the corresponding data at the DRAM interface. X-Ref Target - Figure 1-80 Figure 1-80: Data at the DRAM Interface for 2:1 Mode Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 170 Controller sends the command to the PHY, it strobes app_ref_ack for one cycle, after which another request can be sent. Figure 1-83 illustrates the interface. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 171 ZQ command. Timing parameters must be considered for each pending request when determining when to strobe app_zq_req to achieve the desired interval if precision timing is desired. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 172 If use_addr is asserted but accept is not, the request is not accepted and must be repeated. This behavior is shown Figure 1-86. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 173 1-87. Write data must be supplied in the same clock cycle that wr_data_en is asserted. X-Ref Target - Figure 1-87 Figure 1-87: Command Processing Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 174 At the end of calibration the PHY asserts the init_calib_complete signal output to the Memory Controller. The assertion of this signal indicates that the Memory Controller can begin normal memory transactions. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 175 Note that the following inputs have to be tied to logic “1.” IMPORTANT: assign mc_reset_n = 1'b1; assign mc_cmd_wren = 1'b1; assign mc_ctl_wren = 1'b1; Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 176 Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution X-Ref Target - Figure 1-88 Figure 1-88: PHY Interface Example Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 177 7 and nCK_PER_CLK = 4. The selected slot number can be 1 or 3. Write data offset = CWL + slot number + 2 = 7 + 1 + 2 = 10 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 178 = 10. For a selected slot number of 1, nCK_PER_CLK of 4, the read data offset is: Read data offset = Calibrated PHY read data offset + slot number = 10 + 1 = 11 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 179 (CL – 1 or CL – 2) is preferred after the completion of calibration, the controller must issue the appropriate MRS command. Furthermore, the mentioned data offset must be recalculated with the addition of the AL value. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 180: Customizing The Core
This is the number of unique CS outputs to This option is based on the selected CS_WIDTH memory. MIG tool configuration. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 181 STARVE_LIMIT 1, 2, 3, ... 10 itself high priority. The actual number of lost arbitrations is STARVE_LIMIT × nBANK_MACHS. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 182 This is the memory tCK clock period (ps). on the selected frequency in the MIG tool. Differential termination for system DIFF_TERM_SYSCLK “TRUE,” “FALSE” clock input pins. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 183 FPGA speed grade. The values for these parameters are embedded in the memc_ui_top IP core and should not be modified in the top-level. Xilinx strongly recommends that the MIG tool be rerun for different configurations. RECOMMENDED: Table 1-65: Embedded 7 Series FPGAs Memory Solution Configuration Parameters...
Page 184 This option enables or disables the “ON” IBUF_LPWR_MODE low-power mode for the input buffers. “OFF” This option enables or disables the IDELAY “ON” IODELAY_HP_MODE high-performance mode. ”OFF” Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 185 This option enables or disables the “ON” IBUF_LPWR_MODE low-power mode for the input buffers. “OFF” This option enables or disables the IDELAY “ON” IODELAY_HP_MODE high-performance mode. ”OFF” Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 186 VCO output divisor for PLL outputs. CLKOUT1_DIVIDE, This value is set by the MIG tool – CLKOUT2_DIVIDE, based on the frequency of CLKOUT3_DIVIDE operation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 187 APP_DATA_WIDTH payload data width in the UI. 2 x nCK_PER_CLK x PAYLOAD_WIDTH This UI_INTFC parameter specifies the APP_MASK_WIDTH payload mask width in the UI. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 188 Table 1-66 contains parameters set up by the MIG tool based on the pinout selected. When making pinout changes, Xilinx recommends rerunning the MIG tool to set up the parameters properly. See Bank and Pin Selection Guides for DDR3 Designs, page 193 Bank and Pin Selection Guides for DDR2 Designs, page 203.
Page 189 8'h13: CK/CK# placed in bank 1, byte lane 0. based on the pinout and should not be changed 8'h20: CK/CK# placed in bank 2, byte lane 3. manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 190 See ADDR_MAP See the ADDR_MAP example. description. This parameter varies based on the pinout and should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 191 WE command. See the ADDR_MAP description. WE_MAP This parameter varies See the ADDR_MAP example. based on the pinout and should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 192: Design Guidelines
Memory types, memory parts, and data widths are restricted based on the selected FPGA, FPGA speed grade, and the design frequency. The final frequency ranges are subject to characterization results. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 193 Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and certain rules must be followed to use the DDR3 SDRAM physical layer. Xilinx 7 series FPGAs have dedicated logic for each DQS byte group. Four DQS byte groups are available in each 50-pin bank.
Page 194 The exception is a 16-bit interface in a single bank where there might not be pins available for the clock input. In this case, the clock input needs to come from an adjacent bank Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 195 7 Series FPGAs Data Sheets [Ref 13]. For more information on VCCAUX_IO, see 7 Series SelectIO™ Resources User Guide (UG471) [Ref 2], “VCCAUX_IO” section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 196 HP banks, DCI should be used. For best performance in HR banks, IN_TERM (internal termination) should be used. X-Ref Target - Figure 1-91 Figure 1-91: 40Ω Termination to V Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 197 The allowable distance can be determined by simulation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 198 These rules indicate the maximum electrical delays between DDR3 SDRAM signals: • The maximum electrical delay between any DQ or DM and its associated DQS/DQS# must be ≤ ±5 ps. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 199 – – – – 1,333 1,333 63.7 50.7 32.5 – – 1,066 150.0 144.7 126.4 98.9 63.9 – 150.0 150.0 150.0 150.0 150.0 150.0 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 200 – – – 1,600 1,333 150.0 150.0 150.0 130.2 – – 1,066 150.0 150.0 150.0 150.0 150.0 – 150.0 150.0 150.0 150.0 150.0 150.0 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 201 (sys_clk) and I/O delay reference clock (clk_ref). These standards can be changed, as required, for the system configuration. These signals are brought out to the top-level for system connection: Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 202 PACKAGE_PIN A9 [get_ports {ddr3_dq[0]}] # PadFunction: IO_L1N_T0_39 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}] set_property SLEW FAST [get_ports {ddr3_dq[1]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}] set_property PACKAGE_PIN A8 [get_ports {ddr3_dq[1]}] Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 203: Pin Assignments
Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and certain rules must be followed to use the DDR2 SDRAM physical layer. Xilinx 7 series FPGAs have dedicated logic for each DQS byte group. Four DQS byte groups are available in each 50-pin bank.
Page 204 (DM), and one remains for other signals in the memory interface. Xilinx 7 series FPGAs have dedicated clock routing for high-speed synchronization that is routed vertically within the I/O banks. Thus, DDR2 memory interfaces must be arranged in the banks vertically and not horizontally.
Page 205 • No other pin swapping is permitted. Internal V Internal V can only be used for data rates of 800 Mb/s or below. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 206 • tg_compare_error – This signal is generated by the example design traffic generator, if read data does not match the write data. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 207 DIFF_SSTL18_II I/O standard (VCCO = 1.8V) to the CCIO pins. Because the same differential input receiver is used for both DIFF_SSTL18_II and LVDS inputs, an LVDS clock Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 208 ODT applies to the DQ, DQS, and DM signals only. If ODT is used, the mode register must be set appropriately to enable ODT at the memory. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 209 If this is expected, the values should be averaged appropriately to decrease the maximum possible performance for the target device. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 210 FVCO. The relationship between the input period and the memory period is InputPeriod = ° (MemoryPeriod × M)/(D × D1). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 211 AC-couples and DC-biases the input signals. The figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input. RDIFF Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 212 The sys_clk can be input on any CCIO in the column where the memory interfaces are located. This includes CCIO in banks that do not contain the memory interfaces, but must be in the same column as the memory interfaces. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 213 Byte Group I/O Type I/O Number Designation – – DQ15 D_11 – DQ14 D_10 – DQ13 D_09 – DQ12 D_08 – DQS1_P D_07 DQS-P Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 214 B_07 DQS-P CK_N B_06 DQS-N B_05 – B_04 – CS_N B_03 – B_02 – B_01 – B_00 – A_11 – A_10 – A_09 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 215 – D_02 – – D_01 – – D_00 – – C_11 – – C_10 – – C_09 – – C_08 – – C_07 DQS-P Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 216 – A_07 DQS-P A_06 DQS-N A_05 – A_04 – A_03 – A_02 – A_01 – A_00 – – – – – DQ31 D_11 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 217 DQ13 B_09 CCIO-P DQ12 B_08 CCIO-N DQS1_P B_07 DQS-P DQS1_N B_06 DQS-N DQ11 B_05 – DQ10 B_04 – B_03 – B_02 – B_01 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 218 DQS-P DQS7_N D_06 DQS-N DQ59 D_05 – DQ58 D_04 – DQ57 D_03 – DQ56 D_02 – D_01 – – D_00 – DQ55 C_11 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 219 – DQ36 A_08 – DQS4_P A_07 DQS-P DQS4_N A_06 DQS-N DQ35 A_05 – DQ34 A_04 – DQ33 A_03 – DQ32 A_02 – A_01 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 220 – C_01 CCIO-P C_00 CCIO-N RAS_N B_11 CCIO-P CAS_N B_10 CCIO-N WE_N B_09 CCIO-P B_08 CCIO-N CK_P B_07 DQS-P CK_N B_06 DQS-N B_05 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 221 – DQ26 D_04 – DQ25 D_03 – DQ24 D_02 – D_01 – – D_00 – DQ23 C_11 – DQ22 C_10 – DQ21 C_09 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 222 – A_08 – DQS0_P A_07 DQS-P DQS0_N A_06 DQS-N A_05 – A_04 – A_03 – A_02 – A_01 – RESET_N A_00 – – – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 223 – DQ49 C_03 CCIO-P DQ48 C_02 CCIO-N C_01 CCIO-P – C_00 CCIO-N DQ47 B_11 CCIO-P DQ46 B_10 CCIO-N DQ45 B_09 CCIO-P DQ44 B_08 CCIO-N Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 224 – DQS8_P D_07 DQS-P DQS8_N D_06 DQS-N DQ67 D_05 – DQ66 D_04 – DQ65 D_03 – DQ64 D_02 – D_01 – – D_00 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 225 B_01 – B_00 – A_11 – A_10 – A_09 – A_08 – A_07 DQS-P A_06 DQS-N A_05 – A_04 – A_03 – A_02 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 226 CCIO-N C_01 CCIO-P – C_00 CCIO-N DQ15 B_11 CCIO-P DQ14 B_10 CCIO-N DQ13 B_09 CCIO-P DQ12 B_08 CCIO-N DQS1_P B_07 DQS-P DQS1_N B_06 DQS-N Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 227 – A_08 – DQS0_P A_07 DQS-P DQS0_N A_06 DQS-N A_05 – A_04 – A_03 – A_02 – A_01 – RESET_N A_00 – – – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 228: Debugging Ddr3/Ddr2 Designs
Answer Records Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.
Page 229: Technical Support
Xilinx provides technical support at Xilinx support web page for this product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: • Implement the solution in devices that are not defined in the documentation.
Page 230 1-96. The Hardware Debug section has a snapshot of the older analyzer version but the debugging steps and data to be captured remain the same. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 231 Figure 1-96: Vivado Analyzer Feature Reference Boards Various Xilinx development boards support MIG IP core that include FPGA interfaces to a DDR SODIMM. These boards can be used to prototype designs and establish that the core can communicate with the system.
Page 232 When applicable, check VRN/VRP resistors. Note the values are not the same as Virtex-6 FPGA. • Look at the clock inputs to ensure they are clean. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 233 If internal V is used, ensure the constraints are set appropriately according to the Xilinx Constraints Guide. When the constraints are applied properly, a note similar to the following appears in the .bgn BitGen report file: There were two CONFIG constraint(s) processed from example_top.pcf.
Page 234 The MIG 7 series designs does not issue a calibration failure during Memory Initialization. All other initialization/calibration stages are reviewed in the following Debugging Calibration Stages section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 235 Signifies the start of the Write Calibration stage of calibration. dbg_wrcal_done Signifies successful completion of the Write Calibration stage of calibration. dbg_wrcal_err Signifies Write Calibration exhibited errors and did not complete. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 236 State variable for the PHY Init state machine. States can be decoded in dbg_phy_init_5_0 the ddr_phy_init module. dbg_rddata_valid_r Asserts when the read data (dbg_rddata_r) is valid. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 237 0 to 1 transition not being detected on DQ. dbg_wl_edge_detect_valid_r Signifies valid time Write Leveling algorithm is searching for edge. dbg_rd_data_edge_detect_r_by_dqs Signifies Write Leveling calibration found the 0 to 1 edge transition. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 238 PHASER_OUT Fine Taps found during Write Leveling for all bytes dbg_phy_wrlvl_155_129 PHASER_OUT Coarse Taps found during Write Leveling for all bytes. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 239 Asserts when the valid pattern is detected on the data and is found to dbg_rdlvl_pat_data_match_r match with the expected pattern sent during read leveling. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 240 Indicates that stage 3 lower and upper limits have been determined. dbg_ocal_stg3_lim_left Stage 3 lower limit. dbg_ocal_stg3_lim_right Stage 3 upper limit. dbg_ocal_center_calib_start OCLKDELAY center calibration start indicator. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 241 Input to select DQS byte for which the ILA displays the tap counts of dbg_dqs PHASER_OUT. For example, set to 4'b0000 to view the results on DQS[0]. vio_modify_enable Table 1-83. vio_data_mode_value Table 1-83. vio_addr_mode_value Table 1-83. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 242 Debug signals from window margin check module. See _chk_win.v file dbg_win_chk for details. win_current_bit Unused for DDR3 Interface win_current_byte[3:0] Table 1-85. win_byte_select Table 1-85. po_win_left_ram_out Table 1-85. po_win_right_ram_out Table 1-85. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 243 CK/Address/Command/Control byte lanes are increased and decreased to improve margin on the read DQS preamble detected. This read data offset is then used during read requests to the PHY_CONTROL block. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 244 = R as the trigger. If this stage completed successfully with the asserting of pi_dqsfound_done = 1, use pi_dqsfound_done = R as the trigger to analyze how the stage completed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 245 During writes, it is CWL+2+slot#. During non-data commands, it is 0. During dbg_data_offset_2 reads, it should match what was found during DQSFOUND calibration (rd_data_offset_ranks). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 246 DQS up to two CK clock cycles. This section shows how to capture the Write Leveling results after each of these adjustments. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 247 “7 Series DDR3 Calibration Results” spreadsheet. Later releases of the MIG tool include results for all DQS byte groups removing the need to use dbg_dqs. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 248 PHASER_OUT Coarse Taps found during Write Leveling. Expected Vivado Logic Analyzer Tool Results X-Ref Target - Figure 1-99 Figure 1-99: Trigger = dbg_wrlvl_done Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 249 “10101010” pattern that is read back during this stage of calibration. The read DQS centering is required for the next stage of calibration, OCLKDELAYED calibration. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 250 Always look at DQ[0] for each component. Memory devices either send the “01010101” or “10101010” pattern on all DQ bits or on DQ[0] as specified by the JEDEC standard. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 251 A2 (must be 1) and WE_N (must be 0). Expected Vivado Logic Analyzer Tool Results X-Ref Target - Figure 1-102 Figure 1-102: Trigger = dbg_rdlvl_done[1] Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 252 Table 1-78: Debug Signals of Interest for OCLKDELAYED Calibration Signal Name Description dbg_oclkdelay_calib_start Signifies the start of the OCLKDELAY stage of calibration. dbg_oclkdelay_calib_done Signifies the end of the OCLKDELAY stage of calibration. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 253 The following data patterns might be seen: • On-time write pattern read back – FF00AA5555AA9966 • One CK early write pattern read back – AA5555AA9966BB11 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 254 Data pattern received on rising edge 0. dbg_wcal_mux_rd_fall0_r Data pattern received on falling edge 0. dbg_wcal_mux_rd_rise1_r Data pattern received on rising edge 1. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 255 If the DQ-DQS alignment looks correct, next observe the WE_N to DQS relationship at the memory during a write again using high quality scope and probes. The WE_N to DQS delay must equal the CAS Write Latency (CWL). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 256 6. If the DQS-to-DQ, CWL, and DQS-to-CK look correct, review the above Debugging MPR Read Leveling Failures – DDR3 Only (dbg_rdlvl_err[1] = 1) section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 257 Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution Expected Vivado Logic Analyzer Tool Results X-Ref Target - Figure 1-103 Figure 1-103: Trigger = dbg_wrcal_done Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 258 Debug • If this stage of calibration failed with the assertion of dbg_rdlvl_err[0], set the ILA trigger to dbg_rdlvl_err[0]. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 259 Determine which stage is failing by observing cal1_state_r. • Look at idelay_tap_cnt for each byte group. The idelay_tap_cnt across the DQS byte groups should only vary by 2 to 3 taps. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 260 CWL again using dbg_rdlvl_start[0] as a trigger. Expected Vivado Logic Analyzer Tool Results X-Ref Target - Figure 1-105 Figure 1-105: Trigger = dbg_rdlvl_done[0] Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 261 Signifies data comparison failure due to a read data pattern Signifies the internal counter which tracks PHASER_IN fine tap prbs_dqs_tap_cnt_r movement. pi_counter_read_val Signifies DQS PHASER_IN fine tap setting. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 262 Signifies the data mismatch happened for all bits in a byte. right_edge_found Indicates the right edge of the byte is found. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 263 This allows comparison of expected and actual data when errors occur. The following section details the critical step in Data Error debug. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 264 • 0x1 = Command type (read/write) as defined by fixed_instr_i vio_instr_mode_value • 0x2 = Random read/write commands • 0xE = Write only at address zero • 0xF = Read only at address zero Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 265 Signifies that the read data is valid. cmp_data_valid Signifies the compare data is valid. cmp_error Signifies the cmp_data is not the same as the readback data from memory. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 266 • Determine what type of data error is being seen (bit or byte errors). a. Set the ILA trigger to cmp_error = 1. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 267 Determine if the error is correctable. Rewriting, rereading, resetting, and recalibrating. ° vio_pause_traffic should be asserted and deasserted each time the VIO inputs are Note: changed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 268 = 8 vio_instr_mode_value = 1 vio_fixed_instr_value = 0 (Write Only) vio_data_mode_value = 1 vio_pause_traffic = 0 4. Set the VIO cores to: vio_pause_traffic = 1 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 269 DQ. If the alignment is not correct, focus on the debugging OCLKDELAYED Calibration, page 150. • For debugging purposes only, use ODELAY to vary the phase of DQ relative to DQS. Analyze read timing: Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 270 The automated window checking is enabled by asserting win_start with a single pulse. win_active should then assert until all byte groups have been measured. win_sel_pi_pon must be set to 0x1 to enable Read window measurement. and Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 271 Follow these sections to capture and then analyze the calibration results. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 272 Check that the ACLK inputs are connected and toggling. • Check that the AXI4-Stream waveforms are being followed. • Check core configuration. • Add appropriate core specific checks. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 273 DDR3/DDR2 SDRAM does not generate clock constraints in the XDC file for the No Buffer configurations. You must take care of the clock constraints for the No Buffer configurations in the IP flow. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 274: Introduction
Xilinx 7 Series FPGA Data Sheets [Ref 13] and the Zynq-7000 AP SoC and 7 Series FPGAs Memory Interface Solutions Data Sheet (DS176) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 275: Using Mig In The Vivado Design Suite
2. To create a new project, click the Create New Project option shown in Figure 2-1 open the page as shown in Figure 2-2. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 276 Project Location. Based on the details provided, the project is saved in the directory. X-Ref Target - Figure 2-3 Figure 2-3: Project Name Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 277 (Figure 2-4). Select the Project Type as RTL Project because MIG deliverables are RTL files. X-Ref Target - Figure 2-4 Figure 2-4: Project Type Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 278 If the project was not created earlier, proceed to the next page. X-Ref Target - Figure 2-5 Figure 2-5: Add Sources Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 279 IP files are automatically added to the project. If the IP was not created earlier, proceed to the next page. X-Ref Target - Figure 2-6 Figure 2-6: Add Existing IP (Optional) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 280 Proceed to the next page if the constraints file does not exist. X-Ref Target - Figure 2-7 Figure 2-7: Add Constraints (Optional) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 281 The Default Part page appears as shown in Figure 2-8. X-Ref Target - Figure 2-8 Figure 2-8: Default Part (Default Window) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 282 Figure 2-9: Default Part (Customized Window) Apart from selecting the parts by using the Parts option, parts can be selected by choosing the Boards option, which brings up the evaluation boards supported by Xilinx (Figure 2-10). With this option, a design can be targeted for the various evaluation boards.
Page 283 2-11). This includes the summary of selected project details. X-Ref Target - Figure 2-11 Figure 2-11: New Project Summary 10. Click Finish to complete the project creation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 284 X-Ref Target - Figure 2-12 Figure 2-12: IP Catalog Window – Memory Interface Generator 13. Select MIG 7 Series to open the MIG tool (Figure 2-13). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 285 Component Name field (Figure 2-14). 2. Choose the number of controllers to be generated. This selection determines the replication of further pages. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 286 This name should always start with an alphabetical character and can end with an alphanumeric character. When invoked from Xilinx Platform Studio (XPS), the component name is corrected to be the IP instance name from XPS. 3. Click Next to display the Pin Compatible FPGAs page.
Page 287 This page displays all memory types that are supported by the selected FPGA family. 1. Select the QDR II+ SRAM controller type. 2. Click Next to display the Controller Options page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 288 Chapter 2: QDR II+ Memory Interface Solution X-Ref Target - Figure 2-16 Figure 2-16: Memory Selection Page QDR II+ SRAM designs do not support memory-mapped AXI4 interfaces. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 289 Data Width – The data width value can be selected here based on the memory part selected. The MIG tool supports values in multiples of the individual device data widths. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 290 PHY control block and data input path across asynchronous IN_FIFO. Xilinx recommends adding five additional clocks to the minimum latency measured to Note: determine the actual fixed latency value to be used. If Fixed Latency Mode is not used, the core uses the minimum number of cycles through the system.
Page 291 5. Click Next to display the FPGA Options page. Memory Options Figure 2-20 shows the Memory Options page. X-Ref Target - Figure 2-20 Figure 2-20: Memory Options Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 292 IBUFs not instantiated for the sys_clk_i signal. So for No Buffer scenarios, sys_clk_i signal needs to be connected to an internal clock. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 293 I/O usage. Internal V should only be used for data rates of 800 Mb/s or below. Click Next to display the Extended FPGA Options page. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 294 40, 50, or 60Ω or disabled. This termination is for the read datapath from the QDR II+ SRAM. This selection is only for High Range banks. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 295 Click Validate to check against the MIG pinout rules. You cannot proceed until the MIG DRC has been validated by clicking Validate. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 296 For devices implemented with SSI technology, the SLRs are indicated by a number in the header in each bank, for example, SLR 1. Interfaces cannot span across Super Logic Regions. Not all devices have Super Logic Regions. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 297 Chapter 2: QDR II+ Memory Interface Solution X-Ref Target - Figure 2-25 Figure 2-25: Bank Selection Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 298 A single input or a differential pair can be selected based on the System Clock selection in the FPGA Options page (Figure 2-21). The I/O standard is selected in a similar way as sys_clk above. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 299 This page provides the complete details about the 7 series FPGA memory core selection, interface parameters, Vivado IP catalog options, and FPGA options of the active project. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 300 After generating the design, the MIG GUI closes. Finish After the design is generated, a README page is displayed with additional useful information. Click Close to complete the MIG tool flow. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 301 1. After clicking Generate, the Generate Output Products window appears. This window has the Out-of-Context Settings as shown in Figure 2-28. X-Ref Target - Figure 2-28 Figure 2-28: Generate Output Products Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 302 3. MIG designs comply with “Hierarchical Design" flow in Vivado. For more information, see the Vivado Design Suite User Guide: Hierarchical Design (UG905) [Ref 5] and the Vivado Design Suite Tutorial: Hierarchical Design (UG946) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 303 IP Sources view in the Sources window. Double-clicking on any module or file opens the file in the Vivado Editor. These files are read only. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 304 6. All MIG generated user design RTL and XDC files are automatically added to the project. If files are modified and you wish to regenerate them, right-click the XCI file and select Generate Output Products (Figure 2-32). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 305 7. Clicking the Generate Output Products option brings up the Manage Outputs window (Figure 2-33). X-Ref Target - Figure 2-33 Figure 2-33: Generate Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 306 9. The Vivado Design Suite supports the Open IP Example Design flow. To create the example design using this flow, right-click the IP in the Source Window, as shown in Figure 2-35 and select. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 307 This launches a new Vivado project with all example design files and a copy of the IP. This project has example_top as the Implementation top directory, and sim_tb_top as the Simulation top directory, as shown in Figure 2-36. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 308 Right-click the XCI file and click Recustomize IP (Figure 2-37) to open the MIG GUI and regenerate the design with the preferred options. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 309 The output directory structure of the selected Memory Controller (MC) design from the MIG tool is shown here. There are three folders created within the <component name> directory: • docs • example_design • user_design Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 310 Table 2-1: Files in example_design/rfl Directory Name Description This top-level module serves as an example for connecting the user design to example_top.v the 7 series FPGA memory interface core. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 311 1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of memc_traffic_gen in generated output is now mig_7series_v4_1_memc_traffic_gen. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 312 The top-level wrapper file serves as an example for connecting the user_design to the 7 series FPGA memory interface core. user_design/rtl/clocking Table 2-4 lists the files in the user_design/rtl/clocking directory. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 313 This module is the parameterizable 4-lane PHY in an I/O bank. This module contains the primitive instantiations required within qdr_rld_byte_lane.v an output or input byte lane. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 314 XDC does not adhere to the uniqueness property. • Verified common rules: The interface can span across a maximum of three consecutive banks. ° Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 315 Verified address pin rules: Address signals cannot mix with data bytes except for the qdriip_dll_off_n ° signal. It can use any number of isolated byte lanes. ° Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 316 These signals can be allocated in any of the columns (there is no hard requirement because these signals should reside in a memory column); however, it is better to allocate closer to the chosen memory banks. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 317: Core Architecture
X-Ref Target - Figure 2-38 Figure 2-38: High-Level Block Diagram of QDR II+ Interface Solution Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 318 Read Path qdr_cq_n app_rd_data qdr_q phy_top init_calib_complete user_top UG586_c2_35_090911 Figure 2-39: Components of the QDR II+ SRAM Memory Interface Solution Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 319 Read Address. This bus provides the address to app_rd_addr1[ADDR_WIDTH – 1:0] Input use for a read request. It is valid when app_rd_cmd1 is asserted. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 320 Write Data. This bus provides the data to use app_wr_data1[DATA_WIDTH × 2 – 1:0] Input for a write request. It is valid when app_wr_cmd1 is asserted. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 321 If desired, you can add this functionality. The data returned is not necessarily from the read commands shown in Figure 2-40 and is solely to demonstrate protocol. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 322 Phase Reference Clock from the PLL – The phase reference clock is used in the read banks, and is generated using the memory read clock (CQ/CQ#) routed internally and provided to the Phaser logic to assist with data capture. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 323 IDELAYCTRL module. If a PLL clock drives the IDELAYCTRL input clock, the PLL lock signal needs to be incorporated in the rst_tmp_idelay signal inside the IODELAY_CTRL module. This ensures that the clock is stable before being used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 324 QDR Address. This is the address supplied for memory operations. qdr_w_n Output QDR Write. This is the write command to memory. qdr_r_n Output QDR Read. This is the read command to memory. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 325 • I/Os available within each 7 series bank are grouped into four byte groups, where each byte group consists of up to 12 I/Os. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 326 X-Ref Target - Figure 2-43 Figure 2-43: High-Level PHY Block Diagram for a 36-Bit QDR II+ Interface Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 327 FULL flag output from the OUT_FIFO. The clocks required for operating the OUT_FIFOs and OSERDES are provided by the PHASER_OUT. The clocking details of the write paths using PHASER_OUT are shown in Figure 2-44. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 328 Chapter 2: QDR II+ Memory Interface Solution X-Ref Target - Figure 2-44 Figure 2-44: Write Path Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 329 OUT_FIFO need to be constantly enabled. The PHY Control block helps with this requirement. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 330 5'b110xx – PREALL Rank All others – NOP 29:28: ACT Slot 1–ACTRDWR 27: AP Rank Bank 26:25: RDWR Slot Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 331 Data input ports D1/D2 or D3/D4 are clocked in using the clock provided on the CLKDIV input port (clk in this case), and then passed through a parallel-to-serial conversion block. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 332 For more details about the actual calibration and alignment logic, see the Calibration section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 333 Calibration is performed in two stages: 1. Calibration of read clock with respect to Q 2. Data alignment and valid generation Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 334 This is repeated until a data mismatch is found, indicating the detection of a valid data window edge. Complex pattern read calibration stage is added as the last stage of calibration to improve margin. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 335 3. Calibrate the generation of the read valid signal. Using the value determined in the previous step, delay the read valid signal to align with the read data for user. 4. Assert cal_done. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 336 After the right edge of the data window is determined, the centering process of K clock in the window is performed using the PHASER_OUT stage3 delay. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 337: Customizing The Core
This enables or disables high-performance mode within the IODELAY_HP_MODE IODELAY primitive. When set to OFF, the IODELAY operates in low power mode at the expense of performance. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 338 PLLE2 VCO divisor. This value is set by the MIG tool based DIVCLK_DIVIDE – on the frequency of operation. This simulation only parameter is used to speed up FAST SIM_BYPASS_INIT_CAL simulations. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 339 IODELAY_GRP parameter name is mig_7series_0_IODELAY_MIG. Table 2-13 contains parameters set up by the MIG tool based on the pinout selected. When making pinout changes, Xilinx recommends rerunning the MIG tool to set up the parameters properly. See Pinout Requirements, page 344.
Page 340 8 LSBs of the parameter. manually in generated design. 8'h13: K/K# placed in bank 1, byte lane 3. 8'h20: K/K# placed in bank 2, byte lane 0. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 341 See the ADD_MAP description. This WR_MAP See the ADD_MAP example. parameter varies based on the pinout and should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 342: Design Guidelines
FPGA speed grade, and the design frequency. The final frequency ranges are subject to characterization results. For general PCB routing guidelines, see Appendix A, General Memory Routing Guidelines. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 343 K/K# clocks should be ± 15 ps. • The maximum electrical delay between any Q and its associated CQ/CQ# should be ± 15 ps. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 344 Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and certain rules must be followed to use the QDR II+ physical layer. Xilinx 7 series FPGAs have dedicated logic for each byte group. Four byte groups are available in each 50-pin bank.
Page 345 Chapter 2: QDR II+ Memory Interface Solution • Xilinx recommends keeping the system clock pins in the data write bank. Although the MIG allows system clock selection to be in different super logic regions RECOMMENDED: (SLRs), it is not recommended due to the additional clock jitter in this topology.
Page 346 # PadFunction: IO_L13N_T2_MRCC_37 set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}] set_property IOSTANDARD DIFF_HSTL_I [get_ports {sys_clk_n}] set_property PACKAGE_PIN J22 [get_ports {sys_clk_n}] For more information, see the Xilinx Timing Constraints Guide (UG612) [Ref 15]. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 347 Signal Direction I/O Standard qdr_bw_n Output HSTL_I qdr_cq_p, qdr_cq_n Input HSTL_I_DCI qdr_d Output HSTL_I qdr_k_p, qdr_k_n InOut DIFF_HSTL_II qdr_q Input HSTL_I_DCI qdr_r_n Output HSTL_I Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 348 DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the PLLE2 ° parameter. CLKOUT_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4 ° for below 400 MHz operation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 349 The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 350 Interfaces in Single I/O Column – If the memory interfaces are entirely contained within the same I/O column, a common sys_clk can be shared among the interfaces. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 351: Debugging Qdr Ii+ Sram Designs
Careful attention must be given to functional testing through simulation, proper synthesis and implementation, adherence to PCB layout guidelines, and board verification through IBIS simulation and signal integrity analysis. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 352 This design can be used to observe the behavior of the MIG tool design and can also aid in identifying board-related problems. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 353 When the reset is applied and released, the trigger captures the desired ILA results. Simulation Debug Figure 2-49 shows the debug flow for simulation. X-Ref Target - Figure 2-49 Figure 2-49: Simulation Debug Flowchart Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 354 IES and VCS. Simulation Flow Using Vivado Simulator 1. In the Open IP Example Design Vivado project, under Flow Navigator, select Simulation Settings (Figure 2-50). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 355 1 ms (there are simulation RTL directives which stop the simulation after certain period of time, which is less than 1 ms). Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 356 RTL directives which stop the simulation after certain period of time, which is less than 1 ms), set modelsim.simulate.vsim.more_options to -novopt as shown in Figure 2-50. 3. Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 357 1. In the Open IP Example Design Vivado project, under Flow Navigator select Simulation Settings. 2. Select Target simulator as Verilog Compiler Simulator (VCS). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 358 Figure 2-53: Simulation with VCS 4. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulation as shown in Figure 2-51. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 359 Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there are simulation RTL directives which stop the simulation after certain period of time which is less than 1 ms) as shown in Figure 2-54. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 360 For Samsung Memory models appropriate define values should be added to the memory model itself. Vivado settings does not allow applying define values explicitly on memory models. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 361 [Ref 17] and the Synthesis and Simulation Design Guide (UG626) [Ref 18]. For simulator tool support, see the Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions Data Sheet (DS176) [Ref A working example design simulation completes memory initialization and runs traffic in response to the test bench stimulus.
Page 362 This pattern is then continuously read back while the per-bit calibration is completed, as shown in Figure 2-56. X-Ref Target - Figure 2-56 Figure 2-56: Reads for First Stage Read Calibration Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 363 X-Ref Target - Figure 2-58 Figure 2-58: Test Bench Operation After Completion of Calibration Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 364 X-Ref Target - Figure 2-60 Figure 2-60: User Interface Write and Read X-Ref Target - Figure 2-61 Figure 2-61: QDR II+ Interface Write and Read Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 365 However, timing violations might occur, such as when integrating the MIG tool design with your specific application logic. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 366 QDR II+ SRAM design or the UI (backend application) to the MIG tool design. If failures are encountered, you must ensure the build options (that is, XST, MAP, PAR) specified in the file are used. If failures still exist, Xilinx has many resources available to aid in closing timing. The PlanAhead™ tool [Ref 19] improves performance and quality of the entire design.
Page 367 The cmp_err signal can be used to indicate if a single error was encountered or if multiple errors are encountered. With each error encountered, cmp_err is asserted so that the data can be manually inspected to help track down any issues. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 368 When the Debug port is turned on, the inputs are valid and must be driven to a logical value. Driving the signals incorrectly on the debug port might cause the design to fail or have less read data capture margin. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 369 The algorithm shifts the IODELAY values and looks for edges of the data valid window on a per-byte basis as part of the calibration procedure. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 370 8. Decrease the tap values on PHASER_IN using dbg_pi_f_dec back to the starting value. 9. Clear the error recorded previously by asserting vio_dbg_clear_error. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 371 2. The VIO signal dbg_win_active indicates that the automated window check is in progress. The signals dbg_pi_f_inc and dbg_pi_f_dec must not be used when dbg_win_active is asserted. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 372 OFF in the sim_tb_top module of the sim folder, which disables the debug option for functional simulations. These signals and their associated data are described in Table 2-18. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 373 This signal indicates that the latency could not be dbg_error_max_latency Output measured before the counter overflowed. Each device has one error bit. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 374 Reset read level block. dbg_wr_init[31] rst_stg2_r Reset edge and latency calibration logic. All bytes successfully read leveled. Suppress further dbg_wr_init[32] suppress_stg1 read levels. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 375 Previous sample matched. dbg_rd_stage1_cal[96:92] match_out_r idelay of last detected invalid to valid match transition. dbg_rd_stage1_cal[102:97] samp_cnt_r Sample counter. dbg_rd_stage1_cal[108:103] samps_match_r Cumulative sample match count. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 376 Indicates latency has been measured for byte lane 0 dbg_stage2_cal[8] bl4_rd_cmd_int Indicates calibrating for burst length of 4 data words dbg_stage2_cal[9] bl4_rd_cmd_int_r Internal register stage for burst 4 read command Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 377 == 4. Indicates valid ISERDES read data for the byte being dbg_stage2_cal[33] rd3_vld calibrated (indicated by byte_cnt). Only valid for nCK_PER_CLK == 4. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 378 QDR II+ SRAM does not generate clock constraints in the XDC file for the No Buffer configurations. You must take care of the clock constraints for the No Buffer configurations in the IP flow. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 379: Introduction
[Ref ® ® Memory Interface Solutions v4.1 only supports the Vivado Design Suite. The ISE IMPORTANT: Design Suite is not supported in this version. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 380: Using Mig In The Vivado Design Suite
2. To create a new project, click the Create New Project option shown in Figure 3-1 open the page as shown in Figure 3-2. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 381 Project Location. Based on the details provided, the project is saved in the directory. X-Ref Target - Figure 3-3 Figure 3-3: Project Name Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 382 If the project was not created earlier, proceed to the next page. X-Ref Target - Figure 3-5 Figure 3-5: Add Sources Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 383 3-7). If the constraints file exists in the repository, it can be added to the project. Proceed to the next page if the constraints file does not exist. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 384 The Default Part page appears as shown in Figure 3-8. X-Ref Target - Figure 3-8 Figure 3-8: Default Part (Default Window) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 385 Figure 3-9: Default Part (Customized Window) Apart from selecting the parts by using Parts option, parts can be selected by choosing the Boards option, which brings up the evaluation boards supported by Xilinx (Figure 3-10). With this option, design can be targeted for the various evaluation boards.
Page 386 3-11). This includes the summary of selected project details. X-Ref Target - Figure 3-11 Figure 3-11: New Project Summary 10. Click Finish to complete the project creation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 387 3-12) or you can search from the Search tool bar for the string “MIG.” X-Ref Target - Figure 3-12 Figure 3-12: IP Catalog Window – Memory Interface Generator Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 388 Component Name field (Figure 3-14). 2. Choose the number of controllers to be generated. This option determines the replication of further pages. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 389 This name should always start with an alphabetical character and can end with an alphanumeric character. When invoked from Xilinx Platform Studio (XPS), the component name is corrected to be the IP instance name from XPS. 3. Click Next to display the Pin Compatible FPGAs page.
Page 390 This page displays all memory types that are supported by the selected FPGA family. 1. Select the RLDRAM II or RLDRAM 3 controller type. 2. Click Next to display the Controller Options page. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 391 Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions X-Ref Target - Figure 3-16 Figure 3-16: Memory Selection Page RLDRAM II and RLDRAM 3 designs currently do not support memory-mapped AXI4 interfaces. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 392 Custom Part). If a desired part is not available in the list, you can generate or create an equivalent device and then modify the output to support the desired memory device. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 393 This feature allows the selection of various memory mode register values, as supported by the controller specification (Figure 3-19). X-Ref Target - Figure 3-19 Figure 3-19: Memory Options Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 394 Output Driver Impedance Control – Not available for RLDRAM II. MRS setting in the DRAM that selects the impedance of the output buffers during reads. Click Next to display the FPGA Options page. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 395 Period is between 5,025 ps (199 MHz) and 4,975 ps (201 MHz). When the No Buffer option is selected, IBUF primitives are not instantiated in RTL code and pins are not allocated for the reference clock. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 396 I/O usage. Internal V should only be used for data rates of 800 Mb/s or below. Click Next to display the Extended FPGA Options page. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 397 This feature allows the selection of bytes for the memory interface. Bytes can be selected for different classes of memory signals, such as: • Address and control signals • Data Read signals • Data Write signals Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 398 SLR 1. Interfaces cannot span across Super Logic Regions. Not all devices have Super Logic Regions. X-Ref Target - Figure 3-22 Figure 3-22: Bank Selection Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 399 A single input or a differential pair can be selected based on the System Clock selection in the FPGA Options page (Figure 3-20). The I/O standard is selected in a similar way as sys_clk above. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 400 (Figure 3-24) provides the complete details about the memory core selection, interface parameters, Vivado IP catalog options, and FPGA options of the active project. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 401 Click Generate to generate the design files. The MIG tool generates two output directories: example_design and user_design. After generating the design, the MIG GUI closes. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 402 1. After clicking Generate, the Generate Output Products window appears. This window has the Out-of-Context Settings as shown in Figure 3-25. X-Ref Target - Figure 3-25 Figure 3-25: Generate Output Products Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 403 3. MIG designs comply with “Hierarchical Design" flow in Vivado. For more information, see the Vivado Design Suite User Guide: Hierarchical Design (UG905) [Ref 5] and the Vivado Design Suite Tutorial: Hierarchical Design (UG946) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 404 IP Sources view in the Sources window. Double-clicking on any module or file opens the file in the Vivado Editor. These files are read only. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 405 6. All MIG generated user design RTL and XDC files are automatically added to the project. If files are modified and you wish to regenerate them, right-click the XCI file and select Generate Output Products (Figure 3-29). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 406 Figure 3-29: Generate RTL and Constraints 7. Clicking Generate Output Products option brings up the Manage Outputs window (Figure 3-30). X-Ref Target - Figure 3-30 Figure 3-30: Generate Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 407 9. The Vivado Design Suite supports Open IP Example Design flow. To create the example design using this flow right-click the IP in the Source Window, as shown in Figure 3-32 and select. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 408 This launches a new Vivado project with all example design files and a copy of the IP. This project has example_top as the Implementation top directory, and sim_tb_top as the Simulation top directory, as shown in Figure 3-33. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 409 Right-click the XCI file and click Recustomize IP (Figure 3-34) to open the MIG GUI and regenerate the design with the preferred options. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 410 The output directory structure of the selected Memory Controller (MC) design from the MIG tool is shown here There are three folders created within the <component name> directory: • docs • example_design • user_design Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 411 Table 3-1: Files in example_design/rtl Directory Name Description This top-level module serves as an example for connecting the user design to example_top.v the 7 series FPGAs memory interface core. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 412 Linux Executable file for simulating the design using VCS simulator. Contains the details and prerequisites for simulating the designs using Mentor readme.txt Graphics Questa Advanced Simulator, IES, and VCS simulators. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 413 1. All file names are prefixed with MIG version number. For example, for the MIG 4.1 release module name of rld_mc in generated output is now mig_7series_v4_1_rld_mc. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 414 This module handles the vector remapping between the rld_phy_byte_lane_map.v mc_phy module ports and the user memory ports. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 415 A pinout is generated independent of MIG or is modified after the design is generated. When a design is generated from MIG, the XDC and HDL code are generated with the correct constraints. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 416 If the selected system clock type is single-ended, you need to check whether the reference voltage pins are unallocated in the bank or the internal V is used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 417 A block diagram of the example design test bench is shown in Figure 3-35. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 418 BEGIN_ADDR user_afifo_aempty rld_phy_top data_empty RLDRAM 3 END_ADDR user_afifo_full nCK_PER_CLK user_afifo_afull user_wdfifo_empty user_wdfifo_aempty user_wdfifo_full user_wdfifo_afull error user_rd_data user_rd_valid Figure 3-35: Synthesizable Example Design Block Diagram Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 419 (R/W, R, W) and addresses are determined by PRBS generator logic in the traffic generator module. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 420 This parameter defines the end boundary Sets the memory end address for the port address space. The END_ADDRESS boundary. least-significant Bits[3:0] of this value are ignored. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 421 • CGEN_ALL (default) – This option turns on all of the options above and allows addr_mode_i, instr_mode_i, and bl_mode_i to select the type of generation during run time. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 422 Select a victim DQ line whose state 0 to NUM_DQ_PINS. SEL_VICTIM_LINE is always at logic High. When value = NUM_DQ_PINS, all DQ pins have the same Hammer pattern. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 423 4: DGEN_NEIGHBOR. All 1s are on the DQ pins during the rising edge of DQS except one pin. The address determines the exception pin location. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 424: Core Architecture
This figure shows both the internal FPGA connections to the client interface for initiating read and write commands, and the external interface to the memory device. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 425 Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions X-Ref Target - Figure 3-37 Figure 3-37: High-Level Block Diagram of RLDRAM II/RLDRAM 3 Interface Solution Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 426 RLDRAM II/RLDRAM 3 protocol and timing requirements. For more details, see the Physical Interface section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 427 Command Bank Address. This is the address user_ba[CMD_PER_CLK × BANK_WIDTH – 1:0] Input to use for a write request. It is valid when user_cmd_en is asserted. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 428 Memory CK Lock Done. The system should be kept in a quiet state until assertion of mem_ck_lock_complete Output mem_ck_lock_complete to ensure minimal noise on the CK being driven to the memory. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 429 The client interface protocol is shown in Figure 3-40 for the RLDRAM II four-word burst architecture. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 430 Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions X-Ref Target - Figure 3-40 Figure 3-40: RLDRAM II Client Interface Protocol (Four-Word Burst Architecture) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 431 The init_calib_complete signal is asserted after the memory initialization procedure and PHY calibration are complete, and the core can begin to service client requests. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 432 Figure 3-42: RLDRAM II Client Interface Protocol (Eight-Word Burst Architecture) The client interface protocol for the RLDRAM 3 eight-word burst architecture is shown in Figure 3-43. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 433 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 434 Phase Reference Clock from the PLL – The phase reference clock is used in the read banks, and is generated using the memory read clock (QK/QK#) routed internally and provided to the Phaser logic to assist with data capture. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 435 IDELAYCTRL module. If a PLL clock drives the IDELAYCTRL input clock, the PLL lock signal needs to be incorporated in the rst_tmp_idelay signal inside the IODELAY_CTRL module. This ensures that the clock is stable before being used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 436 Data Mask DM. This is the active-High mask signal, driven by the FPGA to rld_dm Output mask data that a user does not want written to the memory during a write command. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 437 Two refresh commands are issued by asserting cs0/1, ref0/1, and ba0/1. The refresh commands can be issued in the same clock cycle as long as the memory banking rules are met. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 438 Table 3-13: RLDRAM II Command to Write Enable Timing Command to Write Address Multiplexing Configuration Enable (Clock Cycles) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 439 For better throughput, changes in the command bus should be minimized when possible. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 440 • I/Os available within each FPGA bank are grouped into four byte groups, where each byte group consists of up to 12 I/Os. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 441 FPGA logic. Pinout Requirements, page 467 explains the rules that need to be followed when placing the memory interface signals inside the byte groups. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 442 Read latency is measured from the point where the read command is accepted by the user or native interface. Simulation should be run to analyze read latency. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 443 OCLK_DELAYED, is an adjustable phase-shifted output with respect to the byte clock (OCLK) and is used to generate the write clock (DK/DK#) to the memory. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 444 The PHY Control block is used to ensure proper start-up of all PHASER_OUT_PHY blocks used in the interface as well as to control the 3-state timing for RLDRAM 3 operation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 445 (CK/CK# for address/control signals, DK/DK# for data and data mask). For this reason, the PHASER_OUT_PHY block is also used in conjunction with the OSERDES to achieve center alignment. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 446 FPGA logic half-frequency clock and that read data from all the byte groups have the same delay. More details about the actual calibration and alignment logic is explained in the Calibration section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 447 RLDRAM II and RLDRAM 3. In simulation some of the steps are skipped to speed up the time required before processing user commands. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 448: Implementation Details
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 449 This enables the calibration logic to accurately center the clock within the data window. Figure 3-53 shows this example. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 450 The calibration logic determines the best possible delays, based on the initial clock-data alignment. The algorithm first delays the read capture clock using the PHASER_IN fine delay line until a data window edge is detected. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 451 FPGA logic by a memory clock cycle each time the pulse is issued to ensure proper alignment of all captured data in the expected order. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 452 Figure 3-54 shows the RLDRAM II pinout block diagram with two data byte lanes and the overview for the steps taken for write calibration. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 453 The write clock DK is adjusted in relation to the DQ to find the data valid window and center in that window as shown in Figure 3-55. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 454 RLDRAM II write calibration for in which the entire byte lane is shifted in relation to the CK to sweep and find where the write data transfer breaks for the DK-to-CK alignment. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 455 RLDRAM II write calibration, where the byte lanes that do not share a DK clock as part of their PHASER_OUT output, are calibrated with respect to the DK clock in another byte lane. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 456 (DQ moved, stage 2) PHASER_OUT Stage 2 Stage 3 Data Bank PHASER_OUT Stage 2 Stage 3 Figure 3-58: RLDRAM 3 Write Calibration Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 457 DRAM matches what is programmed in the MRS register. For more details, see Debugging RLDRAM II and RLDRAM 3 Designs, page 481. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 458: Customizing The Core
Physical Memory address bus width when using Address RLD_ADDR_WIDTH 11, 18–22 Multiplexing mode. RLDRAM II: 3 BANK_WIDTH Memory bank address bus width. RLDRAM 3: 4 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 459 IODELAY_GRP – when multiple IP cores are used in the design. Reference clock frequency for IDELAYCTRLs. This REFCLK_FREQ 200.0 parameter should not be changed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 460 – the frequency of operation. PLL VCO divisor. This value is set by the MIG tool based on DIVCLK_DIVIDE – the frequency of operation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 461 IODELAY_GRP parameter name is mig_7series_0_IODELAY_MIG. Table 3-15 contains parameters set up by the MIG tool based on the pinout selected. When making pinout changes, Xilinx recommends rerunning the MIG tool so the parameters are set up properly; otherwise see Pinout Requirements, page 467.
Page 462 2 (bank above) to indicate in which bank the clock is placed. This parameter varies based on the pinout and should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 463 3, at location 5. Only the CK_P location is denoted, with the CK_N located on the corresponding N-side location of an I/O pin pair. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 464 See CS_MAP description. This parameter WE_MAP See the CK_MAP example. varies based on the pinout and should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 465 This parameter See the CK_MAP example. DATA4_MAP, varies based on the pinout and DATA5_MAP, should not be changed manually in DATA6_MAP, generated design. DATA7_MAP Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 466: Design Guidelines
For example, to obtain the package delay information for the 7 series FPGA XC7K160T-FF676, this command should be issued: link_design -part xc7k160tfbg676 write_csv flight_time Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 467 Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and certain rules must be followed to use the RLDRAM II/RLDRAM 3 physical layer. Xilinx 7 series FPGAs have dedicated logic for each byte group. Four byte groups are available in each 50-pin bank.
Page 468 QK/QK# clocks must be placed on MRCC pins in a given data bank or in the bank above or below the data. Xilinx 7 series FPGAs have dedicated clock routing for high-speed synchronization that is routed vertically within the I/O banks. Thus, RLDRAM II interfaces must be arranged in the banks vertically and not horizontally.
Page 469 If DM pins are not used, they should be tied to ground. For more information, see the RECOMMENDED: memory vendor data sheet. • Xilinx recommends keeping all of the data generated from a single memory component within a bank. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 470 Settings related to the overall PLL behavior and the used outputs must not be disturbed. A PLL cannot be shared among interfaces. Clocking Architecture, page 434 for information on allowed PLL parameters. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 471 COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 472 # PadFunction: IO_L13N_T2_MRCC_37 set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}] set_property IOSTANDARD DIFF_HSTL_I [get_ports {sys_clk_n}] set_property PACKAGE_PIN J22 [get_ports {sys_clk_n}] For more information, see the Xilinx Timing Constraints Guide (UG612) [Ref 15]. For RLDRAM II interfaces that have the memory system input clock (sys_clk_p/sys_clk_n) placed on CCIO pins within one of the memory banks, MIG assigns the DIFF_HSTL_I I/O standard (VCCO = 1.5V) to the CCIO pins.
Page 473 Table 3-17. Table 3-17: Parameters for Example RLDRAM II Data Byte Lane #1 Parameter Value DK_MAP 8'h00 DQTS_MAP 12'h00A PHY_0_BITLANES 12'h1FF DATA0_MAP 108'h008_007_006_005_004_003_002_001_000 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 474 3-19. Table 3-19: Parameters for Example RLDRAM II Data Byte Lane #3 Parameter Value DM_MAP 12'h01A DQTS_MAP 12'h01B PHY_0_BITLANES 12'h5FF DATA1_MAP 108'h018_017_016_015_014_013_012_011_010 QK_MAP 8'h01 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 475 Table 3-21. Table 3-21: Parameters for Example RLDRAM II Data Byte Lane #4 Parameter Value DQTS_MAP 12'h02A PHY_0_BITLANES 12'hBFC DATA1_MAP 108'h029_028_027_026_02B_025_024_023_022 QK_MAP 8'h02 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 476 7 series FPGAs. These standards should not be changed. Table 3-24 Table 3-25 contain a list of the ports with the I/O standard used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 477 Read Clock (QK_P and QK_N) in the High-Performance banks. In the High-Range banks for RLDRAM II, the MIG tool uses the HSTL_II and DIFF_HSTL_II standards with the internal termination (IN_TERM) attribute chosen in the GUI. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 478 PLL, the CMT backbone must be used. With the MIG implementation, one spare interconnect on the backbone is available that can be used for this purpose. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 479 The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific device family data sheet. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 480 The sys_clk can be input on any CCIO in the column where the memory interfaces are located. This includes CCIO in banks that do not contain the memory interfaces, but must be in the same column as the memory interfaces. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 481: Debugging Rldram Ii And Rldram 3 Designs
Details are provided on: • Functional verification using the UNISIM simulation models • Design implementation verification • Board layout verification Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 482 Vivado logic analyzer feature. Selecting this option port maps the debug signals to VIO modules of the Vivado logic analyzer feature in the design top module. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 483 Vivado IDE. Other simulation tools can be used for MIG IP core simulation but are not specifically IMPORTANT: verified by Xilinx. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 484 IES and VCS. Simulation Flow Using Vivado Simulator 1. In the Open IP Example Design Vivado project, under Flow Navigator, select Simulation Settings (Figure 3-64). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 485 1 ms (there are simulation RTL directives which stop the simulation after certain period of time, which is less than 1 ms). Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 486 -novopt as shown in Figure 3-64. c. Under Compilation tab, set modelsim.compile.vlog.more_options to -sv (only for RLDRAM 3 designs). 3. Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 487 1. In the Open IP Example Design Vivado project, under Flow Navigator select Simulation Settings. 2. Select Target simulator as Verilog Compiler Simulator (VCS). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 488 Figure 3-67: Simulation with VCS 4. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulation as shown in Figure 3-65. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 489 Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there are simulation RTL directives which stop the simulation after certain period of time which is less than 1 ms) as shown in Figure 3-68. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 490 [Ref 17] and the Synthesis and Simulation Design Guide (UG626) [Ref 18]. For simulator tool support, see the Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions Data Sheet (DS176) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1...
Page 491 Write data is not accepted. user_rd_valid Asserted when user_rd_data is valid. user_rd_data Read data returned from the memory as a result of a read command. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 492 0_F_0_F_0_F_F_0. The data pattern is first written to the memory, as shown in Figure 3-69. X-Ref Target - Figure 3-69 Figure 3-69: Writes for First Stage Read Calibration Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 493 The data pattern is first written to the memory, and then read back for the read enable calibration, as shown in Figure 3-71. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 494 After the third stage calibration completes, init_calib_complete is asserted, signifying successful completion of the calibration process. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 495 UI signals in the Objects window, as shown in Figure 3-74. Highlight the user interface signals noted in Table 3-26, page 491, right-click, and select Add > To Wave > Selected Signals. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 496 X-Ref Target - Figure 3-75 Figure 3-75: User Interface Write X-Ref Target - Figure 3-76 Figure 3-76: User Interface Read Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 497 However, timing violations might occur, such as when integrating the MIG tool design with your specific application logic. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 498 RLDRAM II design or the UI (backend application) to the MIG tool design. If failures are encountered, you must ensure the build options (that is, XST, MAP, PAR) specified in the file are used. If failures still exist, Xilinx has many resources available to aid in closing timing. The PlanAhead™ tool [Ref 19] improves performance and quality of the entire design.
Page 499 With each error encountered, dbg_cmp_err is asserted so that the data can be manually inspected to help track down any issues. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 500 Vary the IDELAY/PHASER_IN taps after calibration for the bits that are returning bad ° data. This affects only the read capture timing. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 501 Calibration, page 452. Stage 1 read calibration start Check results of write dbg_phy_status[9] rdlvl_stg1_start signal calibration Stage 1 read calibration is dbg_phy_status[10] rdlvl_cal_done complete Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 502 Control bank address bus used for debug dbg_phy_ba[nCK_PER_CLK × BANK_WIDTH × 2 – 1:0] Output with the Vivado logic analyzer feature. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 503 ISERDES clk that is used to capture rising data. This signal increments the PHASER_OUT dbg_po_f_inc Input generated OSERDES clk that is used to capture falling data. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 504 Selects which stage of write calibration to output: dbg_wrcal_po_first_edge, dbg_wrcal_sel_stg[1:0] Input dbg_wrcal_po_second_edge, or dbg_wrcal_po_final. dbg_wrcal[63:0] Output General Debug port for write calibration Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 505 Refresh complete dbg_phy_init_sm[10] stage2_done Stage 2 calibration is complete dbg_phy_init_sm[22:11] refr_cnt Refresh counter dbg_phy_init_sm[26:23] phy_init_ps Previous state of the initialization state machine dbg_phy_init_sm[31:27] Reserved Reserved Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 506 Six bits per lane center results for simple pattern. dbg_rd_stage1_cal[378+:48] cmplx_left_r Six bits per lane left results for complex pattern. dbg_rd_stage1_cal[426+:48] cmplx_right_r Six bits per lane right results for complex pattern. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 507 Indicates valid ISERDES read data for the byte being dbg_stage2_cal[12] fd0_vld calibrated (indicated by byte_cnt) Indicates valid ISERDES read data for the byte being dbg_stage2_cal[13] rd1_vld calibrated (indicated by byte_cnt) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 508 Indicates latency has been measured for byte lane 1 dbg_stage2_cal[36] latency_measured[2] Indicates latency has been measured for byte lane 2 dbg_stage2_cal[37] latency_measured[3] Indicates latency has been measured for byte lane 3 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 509 First edge not a true edge, hit the limit of the PHASER_OUT dbg_wrcal[61] first_edge_eod taps Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 510 4. Assert vio_dbg_clear_error or system reset. 5. Select a given byte lane using dbg_byte_sel. 6. Observe the tap values on PHASER_IN for the selected byte lane using dbg_pi_counter_read_val. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 511 PHASER_IN to check window sizes, so depending on the tap values after calibration, the left edge of the read data window might not be found properly. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 512 Flag to indicate chk_win is active and measuring read window margins. dbg_win_active While active, the state machine has control over the debug port signals. vio_dbg_clear_error Clear error control signal controlled by chk_win. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 513 This allows you to focus in on a given byte lane and capture each time an adjustment is made to the PHASER_OUT. An example of what to look for is shown in Figure 3-79. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 514 CLOCK_DEDICATED_ROUTE constraint must be set to BACKBONE. RLDRAM II/RLDRAM 3 manages these constraints for designs generated with the System Clock option selected as Differential/Single-Ended (at FPGA Options > System Clock). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 515 RLDRAM II/RLDRAM 3 does not generate clock constraints in the XDC file for the No Buffer configurations. You must take care of the clock constraints for the No Buffer configurations in the IP flow. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 516: Introduction
LPDDR2 SDRAM devices. This user guide provides information about using, customizing, and simulating a LPDDR2 SDRAM interface core for 7 series FPGAs. Features Enhancements to the Xilinx 7 series FPGA memory interface solutions from the earlier memory interface solution device families include: •...
Page 517: Using Mig In The Vivado Design Suite
2. To create a new project, click the Create New Project option shown in Figure 4-1 open the page as shown in Figure 4-2. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 518 Project Location. Based on the details provided, the project is saved in the directory. X-Ref Target - Figure 4-3 Figure 4-3: Project Name Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 519 If the project was not created earlier, proceed to the next page. X-Ref Target - Figure 4-5 Figure 4-5: Add Sources Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 520 4-7). If the constraints file exists in the repository, it can be added to the project. Proceed to the next page if the constraints file does not exist. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 521 The Default Part page appears as shown in Figure 4-8. X-Ref Target - Figure 4-8 Figure 4-8: Default Part (Default Window) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 522 Figure 4-9: Default Part (Customized Window) Apart from selecting the parts by using Parts option, parts can be selected by choosing the Boards option, which brings up the evaluation boards supported by Xilinx (Figure 4-10). With this option, design can be targeted for the various evaluation boards.
Page 523 4-11). This includes the summary of selected project details. X-Ref Target - Figure 4-11 Figure 4-11: New Project Summary 10. Click Finish to complete the project creation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 524 4-12) or you can search from the Search tool bar for the string “MIG.” X-Ref Target - Figure 4-12 Figure 4-12: IP Catalog Window – Memory Interface Generator Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 525 1. Select Create Design to create a new Memory Controller design. Enter a component name in the Component Name field (Figure 4-14). 2. Number of controllers supported for LPDDR2 SDRAM is 1. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 526 This name should always start with an alphabetical character and can end with an alphanumeric character. 3. Click Next to display the Pin Compatible FPGAs page. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 527 (Figure 4-15). Xilinx 7 series devices using stacked silicon interconnect (SSI) technology have Super Logic Regions (SLRs). Memory interfaces cannot span across SLRs. If the device selected or a compatible device that is selected has SLRs, the MIG tool ensures that the interface does not cross SLR boundaries.
Page 528 Controller only settings such as ORDERING are not needed in this case, and the defaults can be used. Settings pertaining to the PHY, such as the Clock Period, are used to set the PHY parameters appropriately. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 529 Data Mask – This option allocates data mask pins when selected. This option should be deselected to deallocate data mask pins and increase pin efficiency. This option is disabled for memory parts that do not support data mask. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 530 Custom Part below the Memory Part pull-down menu. A new page appears, as shown Figure 4-19. X-Ref Target - Figure 4-19 Figure 4-19: Create Custom Part Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 531 X-Ref Target - Figure 4-20 Figure 4-20: Setting Memory Mode Options The mode register value is loaded into the load mode register during initialization. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 532 IBUFs not instantiated for the sys_clk_i signal. So for No Buffer scenarios, sys_clk_i signal needs to be connected to an internal clock. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 533 Click Validate to check against the MIG pinout rules. You cannot proceed until the MIG DRC has been validated by clicking Validate. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 534 This feature allows the selection of bytes for the memory interface. Bytes can be selected for different classes of memory signals, such as: • Address and control signals • Data signals Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 535 Select the pins for the system signals on this page (Figure 4-24). The MIG tool allows the selection of either external pins or internal connections, as desired. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 536 Chapter 4: LPDDR2 SDRAM Memory Interface Solution X-Ref Target - Figure 4-24 Figure 4-24: System Pins Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 537 This page provides the complete details about the 7 series FPGA memory core selection, interface parameters, Vivado tool options, and FPGA options of the active project (Figure 4-25). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 538 Agreement box to accept it. If the license agreement is not agreed to, the memory model is not made available. A memory model is necessary to simulate the design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 539 Click Generate to generate the design files. The MIG tool generates two output directories: example_design and user_design. After generating the design, the MIG GUI closes. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 540 1. After clicking Generate, the Generate Output Products window appears. This window has the Out-of-Context Settings as shown in Figure 4-27. X-Ref Target - Figure 4-27 Figure 4-27: Generate Output Products Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 541 Vivado Design Suite Tutorial: Hierarchical Design (UG946) [Ref 4. After generating the MIG design, the project window appears as shown in Figure 4-29. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 542 Vivado Editor. These files are read only. X-Ref Target - Figure 4-30 Figure 4-30: Vivado Tool Project Sources Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 543 X-Ref Target - Figure 4-31 Figure 4-31: Generate RTL and Constraints 7. Clicking Generate Output Products option brings up the Manage Outputs window (Figure 4-32). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 544 8. All user-design RTL files and constraints files (XDC files) can be viewed in the Sources > Libraries tab (Figure 4-33). X-Ref Target - Figure 4-33 Figure 4-33: Vivado Project – RTL and Constraints Files Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 545 This launches a new Vivado project with all example design files and a copy of the IP. This project has example_top as the Implementation top directory, and sim_tb_top as the Simulation top directory, as shown in Figure 4-35. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 546 Right-click the XCI file and click Recustomize IP (Figure 4-36) to open the MIG GUI and regenerate the design with the preferred options. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 547 The output directory structure of the selected Memory Controller (MC) design from the MIG tool is shown here. In the <component name> directory, three folders are created: • docs • example_design • user_design Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 548 Table 4-1: Files in example_design/rtl Directory Name Description This top-level module serves as an example for connecting the user example_top.v design to the 7 series FPGAs memory interface core. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 549 Table 4-3: Files in example_design/par Directory Name Description example_top.xdc This is the XDC for the core and the example design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 550 SIM_BYPASS_INIT_CAL = "FAST" etc. The top-level file <component_name>_mig.v/vhd is used for design synthesis and IMPORTANT: implementation, whereas the top-level file <component_name>_mig_sim.v/vhd is used in simulations. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 551 This is the top-level module of the Memory Controller. This top-level memory interface block instantiates the controller and the mem_intfc.v PHY. rank_cntrl.v This module manages various rank-level timing parameters. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 552 This module is the parameterizable 4-lane PHY in an I/O bank. This module contains the memory initialization and overall master state ddr_phy_init_lpddr2 control during initialization and calibration. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 553 Table 4-10: Modules in user_design/xdc Directory Name Description <component_name>.xdc This is the XDC for the core and the user design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 554 Pins related to one strobe set should reside in the same byte group. ° The strobe pair (DQS) should be allocated to the DQS I/O pair. ° Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 555 Quick Start Example Design Overview After the core is successfully generated, the example design HDL can be processed through the Xilinx implementation toolset. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 556 Figure 4-37: Synthesizable Example Design Block Diagram Figure 4-38 shows the simulation result of a simple read and write transaction between the tb_top and memc_intfc modules. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 557 (R/W, R, W) and addresses are determined by PRBS generator logic in the traffic generator module. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 558 This parameter defines the start boundary Sets the memory start address for the port address space. The BEGIN_ADDRESS boundary. least-significant Bits[3:0] of this value are ignored. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 559 • CGEN_ALL (default): This option powers on all of the options above and allows addr_mode_i, instr_mode_i, and bl_mode_i to select the type of generation during run time. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 560 Select a victim DQ line whose state 0 to NUM_DQ_PINS. SEL_VICTIM_LINE is always at logic High. When value = NUM_DQ_PINS, all DQ pins have the same Hammer pattern. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 561 4: DGEN_NEIGHBOR. All 1s are on the DQ pins during the rising edge of DQS except one pin. The address determines the exception pin location. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 562 0x2000 0x4FFF 0x00002000 0xFFFF8000 0x2000 0x5FFF 0x00002000 0xFFFF8000 0x2000 0x6FFF 0x00002000 0xFFFF8000 0x2000 0x7FFF 0x00002000 0xFFFF8000 0x2000 0x8FFF 0x00002000 0xFFFF0000 0x2000 0x9FFF 0x00002000 0xFFFF0000 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 563 Low. This signal is only used to send write commands to the QDR II+ qdr_wr_cmd_o Output user interface. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 564 • 0x3: SEQUENTIAL address mode. The address is generated from the internal address counter. The increment is determined by the user interface port width. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 565 Input User-defined simple data 2 for simple 8 repeat data pattern. simple_data3[31:0] Input User-defined simple data 3 for simple 8 repeat data pattern. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 566 (by default, the addr_mode_i, instr_mode_i, and bl_mode_i inputs are set to select PRBS mode). Traffic Test Flow 1. The addr_mode_i input is set to the desired mode (PRBS is the default). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 567 ° memory model data mask bit(s) to zero for proper operation. Setting Up for Simulation The Xilinx UNISIM library must be mapped into the simulator. The test bench provided with the example design supports these pre-implementation simulations: • The test bench, along with vendor’s memory model used in the example design •...
Page 568 IES and VCS simulators respectively. Library files should be added to the ies_run.sh and vcs_run.sh files respectively. See the readme.txt file for details regarding simulations using IES and VCS. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 569 1 ms (there are simulation RTL directives which stop the simulation after a certain period of time, which is less than 1 ms). Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 570 RTL directives which stop the simulation after certain period of time, which is less than 1 ms), set modelsim.simulate.vsim.more_options to -novopt as shown in Figure 4-39. 3. Apply the settings and select OK. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 571 1. In the Open IP Example Design Vivado project, under Flow Navigator select Simulation Settings. 2. Select Target simulator as Verilog Compiler Simulator (VCS). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 572 Figure 4-42: Simulation with VCS 4. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulation as shown in Figure 4-40. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 573 Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there are simulation RTL directives which stop the simulation after certain period of time which is less than 1 ms) as shown in Figure 4-43. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 574 5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 575: Core Architecture
LPDDR2 SDRAM. The user FPGA logic connects to the Memory Controller through the user interface. An example user FPGA logic is provided with the core. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 576 IDELAYCTRLs and the usage of the IODELAY_GRP attribute. IDELAYCTRLs need to have only one instantiation of the component with the attribute set properly, and allow the tools to replicate as needed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 577 This UI clock must be a half or quarter of the DRAM clock. init_calib_complete Output PHY asserts init_calib_complete when calibration is finished. ui_clk_sync_rst Output This is the active-High UI reset. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 578 32'h0000_000F. app_wdf_end This input indicates that the data on the app_wdf_data[] bus in the current cycle is the last data for the current request. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 579 This output indicates that the write data FIFO is ready to receive data. Write data is accepted when both app_wdf_rdy and app_wdf_wren are asserted. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 580 The PHY asserts init_calib_complete when calibration is finished. The application has no need to wait for init_calib_complete before sending commands to the Memory Controller. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 581 The bank, row, and column comprise a target address on the memory device for read and write operations. Commands are specified using the cmd[2:0] input to the core. The available read and write commands are shown in Table 4-17. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 582 This input provides the byte enable for wr_data_mask[2 × nCK_PER_CLK × DATA_WIDTH/8 – 1:0] Input the write data. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 583 4-19). These signals are similar to those for processing write commands, except that they transfer data from the memory device to a buffer in the user design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 584 This active-High input requests that a refresh command be issued to the app_ref_req Input DRAM. This active-High output indicates that the Memory Controller has sent the app_ref_ack Output requested refresh command to the PHY interface. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 585 • Internal (FPGA) logic • Write path (output) I/O logic • Read path (input) and delay I/O logic • IDELAY reference clock (200 MHz) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 586 SYSCLKN SYSCLKP MMCM SYSRST PHY Control PHASER_REF Figure 4-45: Clocking Architecture The details of the ISERDES/OSERDES connectivity are shown in Figure 4-50 Figure 4-52. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 587 IDELAYCTRL module. If a PLL clock drives the IDELAYCTRL input clock, the PLL lock signal needs to be incorporated in the rst_tmp_idelay signal inside the IODELAY_CTRL.v module. This ensures that the clock is stable before being used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 588 The Memory Controller block is organized as four main pieces: • Configurable number of “bank machines” • Configurable number of “rank machines” • Column machine • Arbitration block Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 589 A bank machine precharges a DRAM bank as soon as possible unless another pending request targets the same bank. This is discussed in greater detail in the Precharge Policy section. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 590 Arbitration is necessary because several bank machines might request to send row commands (activate and precharge) at the same time. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 591 "Global" in the Generate Output Products settings. After generating the design, the design top-level RTL file should be edited and the ORDERING parameter should be changed to "RELAXED." Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 592 The phaser blocks (PHASER_IN and PHASER_OUT) are multi-stage programmable delay line loops that can dynamically track DQS signal variation and provide precision phase adjustment. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 593 4 or divided by 2 version of the LPDDR2 memory clock. A block diagram of the PHY design is shown in Figure 4-48. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 594 Figure 4-49 shows the overall flow of memory initialization and the different stages of calibration. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 595 PHASER_IN and PHASER_OUT blocks, four IN/OUT_FIFOs, ISERDES, OSERDES, ODDR, IDELAY, and IOBs. A single PHY control block communicates with all four PHASER_IN and PHASER_OUT blocks within the I/O bank. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 596 PHY_Ctl_Full signal is inactive. This active-High output becomes set when the PHY control block is ready PHY_Ctl_Ready Output to start receiving commands. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 597 Seq field. • CAS Slot – The slot number being used by the Memory Controller for write/read (CAS) commands. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 598 This attribute specifies how long in LPDDR2 SDRAM clock cycles after the RD_CMD_OFFSET_1 Vector[5:0] associated read command is executed that the auxiliary output becomes active. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 599 PHY control blocks across multiple I/O banks. The PHY control block, in conjunction with the PHASER_OUT, generates the write DQS and the DQ/DQS 3-state control signals during read and write commands. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 600 PHY control block because the default in the dedicated PHY for address/commands can be set to 0 or 1 as needed. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 601 Figure 4-50: Address/Command Path Block Diagram The timing diagram of the address/command path from the output of the OUT_FIFO to the FPGA pins is shown in Figure 4-51. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 602 FPGA logic to operate at low frequencies up to 1/2 the frequency of the LPDDR2 SDRAM clock. Figure 4-52 shows the block diagram of the datapath. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 603 DQ bit from the calibration logic or Memory Controller and writes the data into the storage array in the PHY_Clk clock domain, which is 1/2 the frequency of the LPDDR2 SDRAM clock. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 604 PHASER_IN block is associated with a group of 12 I/Os. Each I/O bank in the 7 series FPGA has four PHASER_IN blocks, and hence four bytes for LPDDR2 SDRAM can be placed in a bank. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 605 64 taps. After the right noise region is found with FINE taps, proceed to use IDELAY taps to find the start of left noise region by delaying the DATA. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 606 DQS center alignment in the data valid window. X-Ref Target - Figure 4-53 Figure 4-53: Read Leveling Stage 1 Timing Diagram Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 607 Read Leveling calibration stage (initial tap value) and decrements one tap at time until a data mismatch is found when comparing read data with the expected data. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 608 MMCM-generated source capture clock using the fine-phase shift capability of the MMCM. This method allows fine adjustment of the capture clocks of all bytes simultaneously but does not allow control over individual byte clock phase adjustment. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 609 [CA_WIDTH × 2 × mc_ca[2 × CA_WIDTH – 1:0] is the first mc_ca Input – nCK_PER_CLK – 1:0] command address in the sequence of four. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 610 PHY Control FIFOs. The Almost FULL phy_mc_ctl_full Output High flag is asserted when the FIFO is one entry away from being FULL. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 611: Designing With The Core
FIFO interface and always returns the data in order. The native interface offers higher performance in some situations, but is more challenging to use. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 612 Figure 4-56: Memory Address Mapping for Bank-Row-Column Mode in UI Module X-Ref Target - Figure 4-57 Figure 4-57: Memory Address Mapping for Row-Bank-Column Mode in UI Module Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 613 COLUMN Address Bits Bits R14 R13 R12 R11 R10 R9 R1 R0 B2 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 614 For write data that is output after the write command has been registered, as shown in Note 3, the maximum delay is two clock cycles. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 615 Chapter 4: LPDDR2 SDRAM Memory Interface Solution X-Ref Target - Figure 4-59 Figure 4-59: UI Interface Write Timing Diagram (Memory Burst Type = BL8) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 616 Figure 4-61. X-Ref Target - Figure 4-61 Figure 4-61: UI Interface Back-to-Back Write Commands Timing Diagram (Memory Burst Type = BL8) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 617 X-Ref Target - Figure 4-64 Figure 4-64: UI Interface Read Timing Diagram (Memory Burst Type = BL8) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 618 Equation 4-1 shows the ZQ request interval maximum. tZQI tRCD nBANK_MACHS × × Equation 4-1 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 619 If use_addr is asserted but accept is not, the request is not accepted and must be repeated. This behavior is shown Figure 4-68. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 620 The user design can identify when a request is being processed and when it finishes by monitoring the rd_data_en and wr_data_en signals. When the rd_data_en signal is asserted, the Memory Controller has completed processing a read command request. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 621: Customizing The Core
The MIG tool should be used to regenerate a design when parameters need to be changed. The parameters set by the MIG tool are summarized in Table 4-25 Table 4-27. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 622 This is the DRAM component address bus This option is based on the selected ROW_WIDTH width. memory device. DM_WIDTH This is the number of data mask bits. DQ_WIDTH/8 Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 623 This is the memory tCK clock period (ps). on the selected frequency in the MIG tool. Differential termination for system DIFF_TERM_SYSCLK “TRUE,” “FALSE” clock input pins. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 624 FPGA speed grade. The values for these parameters are integrated in the memc_ui_top IP core and should not be modified in the top-level. Xilinx strongly recommends that the MIG tool be rerun for different configurations. RECOMMENDED: Table 4-26: Embedded 7 Series FPGAs Memory Solution Configuration Parameters...
Page 625 This option enables or disables the IDELAY “ON” IODELAY_HP_MODE high-performance mode. ”OFF” This option is set to ON valid when I/O DATA_IO_IDLE_PWRDWN "ON," "OFF” Power reduction option is enabled. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 626 This is ceil(log2(DQ_WIDTH)). This is the supported memory standard for DRAM_TYPE LPDDR2 the Memory Controller. This is the DQ bus width per DRAM DRAM_WIDTH component. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 627 Table 4-27 contains parameters set up by the MIG tool based on the pinout selected. When making pinout changes, Xilinx recommends rerunning the MIG tool to set up the parameters properly. See Bank and Pin Selection Guides for LPDDR2 Designs, page 631.
Page 628 8'h13: CK/CK# placed in bank 1, byte lane 3. based on the pinout and 8'h20: CK/CK# placed in bank 2, byte lane 0. should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 629 This parameter varies See the ADDR_MAP example. DATA5_MAP, based on the pinout and DATA6_MAP, should not be changed DATA7_MAP, manually in generated DATA8_MAP design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 630 CK/CK# in command/address byte group. This parameter varies based on the pinout and should not be changed manually in generated design. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 631: Design Guidelines
Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and certain rules must be followed to use the LPDDR2 SDRAM physical layer. Xilinx 7 series FPGAs have dedicated logic for each DQS byte group. Four DQS byte groups are available in each 50-pin bank.
Page 632 Devices implemented with SSI technology have SLRs. Memory interfaces cannot span across SLRs. Ensure that this rule is followed for the part chosen and for any other pin-compatible parts that can also be used. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 633 Settings related to the overall MMCM behavior and the used outputs must not be disturbed. A MMCM cannot be shared among interfaces. Clocking Architecture, page 585 for information on allowed MMCM parameters. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 634 Capable IOB site that has dedicated fast path to PLL sites within the same clock region. You might want to analyze why this issue exists and correct it. This is normally an ERROR Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 635 VCCAUX_IO NORMAL [get_ports {lpddr2_dq[1]}] set_property SLEW FAST [get_ports {lpddr2_dq[1]}] set_property IOSTANDARD HSUL_12 [get_ports {lpddr2_dq[1]}] set_property PACKAGE_PIN AK11 [get_ports {lpddr2_dq[1]}] For more information, see the Xilinx Timing Constraints User Guide (UG612) [Ref 15]. For LPDDR2 SDRAM interfaces that have the memory system input clock...
Page 636 While applying specific trace-matching guidelines for the LPDDR2 SDRAM interface, this additional package delay term should be considered for the Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 637 DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the MMCME2 ° parameter. CLKOUT_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4 ° for below 400 MHz operation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 638 The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 639 I/O columns. The input clock input must be in the same column as the memory interface to drive the MMCM using the CMT Backbone, which minimizes jitter. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 640 Termination is not required for LPDDR2 memory interfaces. For more information, contact your TIP: memory vendor. The termination guidelines can be used in case termination is required. Internal V is used in this example. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 641 – B_10 – – B_09 – – B_08 – CK_P B_07 DQS-P CK_N B_06 DQS-N – B_05 – – B_04 – CS_N B_03 – Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 642 IODELAY CTRL logic (through an additional MMCM). This clock is not utilized, CLOCK_DEDICADE_ROUTE (as they are limited in number), hence the FALSE value is Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 643 LPDDR2 SDRAM does not generate clock constraints in the XDC file for the No Buffer configurations. You must take care of the clock constraints for the No Buffer configurations in the IP flow. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 644: Introduction
® ® Memory Interface Solutions v4.1 only supports the Vivado Design Suite. The ISE IMPORTANT: Design Suite is not supported in this version. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 645: Using Mig In The Vivado Design Suite
2. To create a new project, click the Create New Project option shown in Figure 5-1 open the page as shown in Figure 5-2. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 646 Project Location. Based on the details provided, the project is saved in the directory. X-Ref Target - Figure 5-3 Figure 5-3: Project Name Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 647 If the project was not created earlier, proceed to the next page. X-Ref Target - Figure 5-5 Figure 5-5: Add Sources Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 648 5-7). If the constraints file exists in the repository, it can be added to the project. Proceed to the next page if the constraints file does not exist. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 649 The Default Part page appears as shown in Figure 5-8. X-Ref Target - Figure 5-8 Figure 5-8: Default Part (Default Window) Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 650 5-10). With this option, designs can be targeted for the various evaluation boards. If the XCI file of an existing IP was selected in an earlier step, the same part should be selected here. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 651 5-11). This includes the summary of selected project details. X-Ref Target - Figure 5-11 Figure 5-11: New Project Summary 10. Click Finish to complete the project creation. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 652 5-12) or you can search from the Search tool bar for the string “MIG.” X-Ref Target - Figure 5-12 Figure 5-12: IP Catalog Window – Memory Interface Generator Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 653 (that is, the selected data width and number of banks). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 654 Chapter 5: Multicontroller Design X-Ref Target - Figure 5-14 Figure 5-14: MIG Output Options Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 655 Select the number of controllers for each memory interface on the Memory Selection page (Figure 5-15). X-Ref Target - Figure 5-15 Figure 5-15: Memory Selection Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 656 The Debug option can be selected for one controller only. Debug logic is generated for the selected controller (Figure 5-16). X-Ref Target - Figure 5-16 Figure 5-16: FPGA Options Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 657 Extended FPGA Options page for a multicontroller design with all three memory interfaces chosen. X-Ref Target - Figure 5-17 Figure 5-17: Extended FPGA Options Page Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 658 One PLL and one MMCM are needed for each controller regardless of system clock pin is shared or not. System clock pin can only be shared and no other resources (PLL or MMCM) are shared across controllers. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 659 1. After clicking Generate, the Generate Output Products window appears. This window has the Out-of-Context Settings as shown in Figure 5-19. X-Ref Target - Figure 5-19 Figure 5-19: Generate Output Products Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 660 Vivado Design Suite Tutorial: Hierarchical Design (UG946) [Ref 4. After generating the MIG design, the project window appears as shown in Figure 5-21. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 661 Vivado Editor. These files are read only. X-Ref Target - Figure 5-22 Figure 5-22: Vivado Tool Project Sources Window Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 662 X-Ref Target - Figure 5-23 Figure 5-23: Generate RTL and Constraints 7. Clicking Generate Output Products option brings up the Manage Outputs window (Figure 5-24). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 663 8. All user-design RTL files and constraints files (XDC files) can be viewed in the Sources > Libraries tab (Figure 5-25). X-Ref Target - Figure 5-25 Figure 5-25: Vivado Project – RTL and Constraints Files Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 664 This launches a new Vivado project with all example design files and a copy of the IP. This project has example_top as the Implementation top directory, and sim_tb_top as the Simulation top directory, as shown in Figure 5-27. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 665 Right-click the XCI file and click Recustomize IP (Figure 5-28) to open the MIG GUI and regenerate the design with the preferred options. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 666 See the appropriate memory interface chapter in this document for more information. The MIG GUI pages that are different for multicontroller designs are explained in this chapter. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 667 All chosen memory interfaces for multicontroller designs are shown here. mig_7series_v4_1 docs example_design traffic_gen synth user_design clocking ddr3_sdram controller ip_top qdriiplus_sram rldram_ii controller ip_top Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 668 2. Invoke Vivado with the same FPGA part settings that the earlier core is generated with. 3. Apply the following command in the Tcl Console of Vivado to create the IP: create_ip -name mig_7series -version <latest version> -vendor xilinx.com -library ip -module_name <component_name>...
Page 669 SYSCLK_C_P SYSCLK_P R692 CLOCK 100K FPGA GENERATOR 1/10W SYSCLK_C_N SYSCLK_N R596 R597 C651 1.00K 1.00K 0.1 µF 1/16W 1/16W UG583_c2_57_060315 Figure A-1: System Clock Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 670: Appendix A: General Memory Routing Guidelines
6. Signal lines must be routed over a solid reference plane. Avoid routing over voids (Figure A-2). X-Ref Target - Figure A-2 UG583_c2_13_050614 Figure A-2: Signal Routing Over Solid Reference Plane Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 671: Appendix A: General Memory Routing Guidelines
8. Keep the routing at least 30 mils away from the reference plane and void edges with the exception of breakout regions (Figure A-2). Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 672 9. In the breakout region, route signal lines in the middle of the via void aperture. Avoid routing at the edge of via voids (Figure A-4). X-Ref Target - Figure A-4 UG583_c2_15_051915 Figure A-4: Breakout Region Routing Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 673 11. Add ground vias as much as possible around the edges of the device and inside the device to make a better ground return path for signals and power, especially corners. Corner or edge balls are generally less populated as grounds. Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016...
Page 674: Appendix A: General Memory Routing Guidelines
1.0 µF capacitor, physically interleaving among resistors, as shown Figure A-6. X-Ref Target - Figure A-6 UG583_c2_17_050614 Figure A-6: Example of V Termination Placement Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 675: Appendix A: General Memory Routing Guidelines
Figure A-7. X-Ref Target - Figure A-7 cmd/addr/ctrl cmd/addr/ctrl routing channel dq routing channel FPGA UG583_c2_18_073014 Figure A-7: Component Placement Recommendations for One Component Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 676: Appendix A: General Memory Routing Guidelines
For five components, the recommendation is shown in Figure A-8. X-Ref Target - Figure A-8 FPGA UG583_c2_19_073014 Figure A-8: Component Placement Recommendations for Five Components Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 Send Feedback UG586 November 30, 2016 www.xilinx.com...
Page 677: Xilinx Resources
Unless otherwise noted, IP references are for the product documentation page. These references provide supplemental information useful for this document: 1. Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions Data Sheet (DS176) 2. 7 Series FPGAs SelectIO™ Resources User Guide (UG471) 3.
Page 678: Please Read: Important Legal Notices
Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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