Xilinx Zynq-7000 User Manual page 507

Table 3-30: Read Stage 1 Debug Signal Map (Cont'd)
Bits
dbg_rd_stage1_cal[474+:48]
dbg_rd_stage1_cal[682+:48]
dbg_rd_stage1_cal[690+:48]
dbg_rd_stage1_cal[698+:48]
dbg_rd_stage1_cal[706+:48]
dbg_rd_stage1_cal[522+:72]
dbg_rd_stage1_cal[594+:72]
dbg_rd_stage1_cal[714+:72]
dbg_rd_stage1_cal[786+:9]
dbg_rd_stage1_cal[795+:8]
dbg_rd_stage1_cal[803+:8]
Read Stage 2 Calibration Debug
Table 3-31 indicates the mapping between bits within the dbg_rd_stage2_cal bus and
debug signals in the PHY. All signals are found within the
qdr_rld_phy_read_stage2_cal module and are all valid in the clk domain.
Table 3-31: Read Stage 2 Debug Signal Map
Bits
dbg_stage2_cal[0]
dbg_stage2_cal[5:1]
dbg_stage2_cal[6]
dbg_stage2_cal[7]
dbg_stage2_cal[8]
dbg_stage2_cal[9]
dbg_stage2_cal[10]
dbg_stage2_cal[11]
dbg_stage2_cal[12]
dbg_stage2_cal[13]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
PHY Signal Name
cmplx_center_r
simp_left_63
cmplx_left_63
simp_right_63
cmplx_right_63
rd_data_lane_r
iserdes_lane_r
cmplx_rd_burst_bytes
bit_comp
simp_min_eye_r
cmplx_min_eye_r
PHY Signal Name
en_mem_latency
latency_cntr[0]
rd_cmd
latency_measured[0]
bl4_rd_cmd_int
bl4_rd_cmd_int_r
edge_adv_cal_start
rd0_vld
fd0_vld
rd1_vld
www.xilinx.com
Description
Six bits per lane center results for complex pattern.
Left edge result is 63 for simple pattern, one bit per
lane.
Left edge result is 63 for complex pattern, one bit per
lane.
Right edge result is 63 for simple pattern, one bit per
lane.
Right edge result is 63 for complex pattern, one bit per
lane.
Aligned PHY data for lane currently undergoing
calibration.
Raw PHY data for lane currently undergoing calibration.
Complex data to compare against memory read data.
Cumulative compare per bit.
Minimum eye detected per lane simple pattern.
Minimum eye detected per lane complex pattern.
Description
Signal to enable latency measurement
Indicates the latency for the first byte lane in the interface
Internal rd_cmd for latency calibration
Indicates latency has been measured for byte lane 0
Indicates calibrating for burst length of 4 data words
Internal register stage for burst 4 read command
Indicates start of edge_adv calibration, to see if the
pi_edge_adv signal needs to be asserted
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt)
507
Send Feedback