Synplify Pro Black Box Testing - Xilinx Zynq-7000 User Manual

Synplify Pro Black Box Testing

Using the Synopsys
black box synthesis with Synplify Pro and implementation with Vivado.
1. Generate the 7 series architecture DDR3 SDRAM IP core with OOC flow to generate the
.dcp file for implementation. The Target Language for the project can be selected as
Verilog or VHDL.
2. Create the example design for the DDR3 SDRAM IP core using the information provided
in the example design section and close the Vivado project.
3. Invoke the Synplify Pro software which supports 7 series FPGA and select the same 7
series FPGA part selected at the time of generating the IP core.
4. Add the following files into Synplify Pro project based on the Target Language selected
at the time of invoking Vivado:
a. For Verilog:
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/ip/<Component_Name>/*stub.v
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/imports/rtl/example_top.v
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/imports/rtl/traffic_gen/*.v
b. For VHDL:
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/ip/<Component_Name>/*stub.vhdl
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/imports/rtl/example_top.vhd
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/imports/rtl/traffic_gen/*.v
5. Specify top-level module/entity name of the design. In this case it is example_top. Run
Synplify Pro synthesis to generate the .edf file. Then, close the Synplify Pro project.
6. Open a new Vivado project with Project Type as Post-synthesis Project and select the
Target Language, same as selected at the time of generating the IP core.
7. Add the Synplify Pro generated .edf file to the Vivado project as Design Source.
8. Add the DDR3 IP .dcp file present inside the example project in step 2 to this Vivado
project as Design Source. For example:
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/sources_1/ip/<Component_Name>/<Component_Name>.dcp
9. Add the .xdc file generated in step 2 to the Vivado project as a constraint file. For
example:
<project_dir>/<Component_Name>_example/
<Component_Name>_example.srcs/constrs_1/imports/par/example_top.xdc
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
® ®
Synplify Pro flow for example_design, follow these steps to run
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