Xilinx Zynq-7000 User Manual page 510

Table 3-32: Write Debug Signal Map (Cont'd)
Bits PHY Signal Name
dbg_wrcal[62] second_edge_eod
po_fine_underflow_check,
dbg_wrcal[63]
po_fine_overflow_check
Margin Check
Debug signals are provided to move either clocks or data to verify functionality and to
confirm sufficient margin is available for reliable operation. These signals can also be used
to check for signal integrity issues affecting a subset of signals or to deal with trace length
mismatches on the board. To verify read window margin, enable the debug port when
generating a design in the MIG tool and use the provided example design. The steps to
follow are:
1. Open the Vivado hardware session and program the FPGA under test with generated BIT
and LTX files.
2. Verify that calibration completes (init_calib_complete should be asserted) and no
errors currently exist in the example design (both tg_compare_error and
dbg_cmp_err should be Low).
3. To measure margin with PRBS8 pattern, set VIO signals with the listed values in the
traffic_gen_top instance in example_top:
vio_modify_enable = 'd1
vio_data_mode_value = 'd7
vio_addr_mode_value = 'd3
vio_instr_mode_value = 'd4
vio_bl_mode_value = 'd2
vio_fixed_bl_value = 'd128
vio_fixed_instr_value = 'd1
vio_data_mask_gen = 'd0
4. Assert vio_dbg_clear_error or system reset.
5. Select a given byte lane using dbg_byte_sel.
6. Observe the tap values on PHASER_IN for the selected byte lane using
dbg_pi_counter_read_val.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Description
Second edge not a true edge, hit the limit of the PHASER_OUT
taps
Check for underflow or overflow on the internal PHASER_OUT
tap counter.
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