Xilinx Zynq-7000 User Manual page 441

• PHASER_IN/PHASER_OUT blocks are available in each byte group and are multi-stage
programmable delay line loops that can provide precision phase adjustment of the
clocks. Dedicated clock structures within an I/O bank, referred to as byte group clocks,
generated by the PHASERs help minimize the number of loads driven by the byte group
clock drivers.
• OUT_FIFO and IN_FIFO are shallow eight or four-deep FIFOs available in each byte
group and serve to transfer data from the FPGA logic domain to the I/O clock domain.
OUT_FIFOs are used to store output data and address/controls that need to be sent to
the memory while IN_FIFOs are used to store captured read data before transfer to the
FPGA logic.
The Pinout Requirements, page 467
placing the memory interface signals inside the byte groups.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
explains the rules that need to be followed when
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