Designing With The Core - Xilinx Zynq-7000 User Manual

Table 1-61: Memory Controller to Calibration Logic Interface Signals (Cont'd)
Signal Name Width
phy_mc_ctl_full 1
phy_mc_cmd_full 1
phy_mc_data_full 1
[2 × nCK_PER_CLK ×
phy_rd_data
DQ_WIDTH – 1:0]
phy_rddata_valid 1
calib_rd_data_offset [6 × RANKS – 1:0]
init_calib_complete 1
Notes:
1. The parameter nCK_PER_CLK defines the number of DDR2 or DDR3 SDRAM clock cycles per PHY_Clk cycle.
2. The parameter ROW_WIDTH is the number of DDR2 or DDR3 SDRAM ranks.
3. The parameter BANK_WIDTH is the number of DDR2 or DDR3 SDRAM banks.
4. The parameter CS_WIDTH is the number of DDR2 or DDR3 SDRAM cs_n signals.
5. The parameter CKE_WIDTH is the number of DDR2 or DDR3 SDRAM CKE signals.
6. The parameter DQ_WIDTH is the width of the DDR2 or DDR3 SDRAM DQ bus.

Designing with the Core

The core is bundled with an example design that can be simulated. The example design can
be used as a starting point for the user design or as a reference for debugging purposes.
Only supported modifications should be made to the configuration of the core. See
Customizing the Core, page 180
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
I/O
To/From Type Description
PHY
Bitwise AND of all the Almost FULL flags of
Active- all the PHY Control FIFOs. The Almost
Output
High FULL flag is asserted when the FIFO is one
entry away from being FULL.
Bitwise OR of all the Almost FULL flags of
Active- all the command OUT_FIFOs. The Almost
Output
High FULL flag is asserted when the FIFO is one
entry away from being FULL.
Bitwise OR of all the Almost FULL flags of
Active- all the write data OUT_FIFOs. The Almost
Output
High FULL flag is asserted when the FIFO is one
entry away from being FULL.
This is the read data from the dedicated
Output – PHY. It is 8x the memory DQ width for a 4:1
clock ratio.
Active- This signal is asserted when valid read
Output
High data is available.
This signal is the calibrated read data
Output – offset value with respect to command 0 in
the sequence of four commands.
This signal is asserted after memory
Active-
Output initialization and calibration are
High
completed.
for supported configuration parameters.
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