Xilinx Zynq-7000 User Manual page 329

The clocking details of the address/control using PHASER_OUT are shown in
X-Ref Target - Figure 2-45
Output Path
Because the address/command and write data are provided by the user backend, the QDR
PHY transfers the signals from the FPGA logic domain to their internal PHASER clock
domain and provides them from the OSERDES to the memory. The OUT_FIFOs are used
mainly as domain transfer elements in the design, and therefore the write and read enables
of the OUT_FIFO need to be constantly enabled. The PHY Control block helps with this
requirement.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 2: QDR II+ Memory Interface Solution
Figure 2-45: Address Path
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Figure 2-45.
329
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