Xilinx Zynq-7000 User Manual page 456

X-Ref Target - Figure 3-57
A/C Bank
Byte lane
with a DK
Starting
(1)
point, 32
taps
Byte lane
Start the
(2)
without a sweep at DQ
0 taps
DK
Sweep until window
(3)
edge found or end
of taps
Final
(4)
Setting
Figure 3-57: RLDRAM II Write Calibration (Stage 3, DK-to-DQ2)
Figure 3-58 shows the RLDRAM 3 pinout with two data byte lanes and the overview for the
steps taken for write calibration.
X-Ref Target - Figure 3-58
A/C Bank
(with CK)
Data Bank
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
CK
DK
DQ
Rise
DQ
Rise
Rise
Data Shift
Fall
DQ
Data Shift
DQ
Rise
PHASER_OUT
Stage 2 Stage 3
PHASER_OUT
Stage 2 Stage 3
PHASER_OUT
Stage 2 Stage 3
Figure 3-58: RLDRAM 3 Write Calibration
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Fall
Fall
Fall
Rise
Fall
Fall
DK
CK
Step 1: Calibrate DQ with the DK in another
byte lane (DQ moved, stage 2)
DQ
DQ
Rise
456
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