Xilinx Zynq-7000 User Manual page 63

Table 1-8: Files in user_design/rtl/phy Directory (Cont'd)
(1)
Name
ddr_phy_dqs_found_cal
ddr_phy_init
ddr_phy_rdlvl
ddr_phy_top
ddr_phy_wrcal
ddr_phy_wrlvl
ddr_prbs_gen
Notes:
1. All file names are prefixed with the MIG core version number. For example, for the MIG 4.1 release module name
of ddr_byte_group_io in generated output is now mig_7series_v4_1_ddr_byte_group_io.
user_design/rtl/ui
This directory contains the user interface code that mediates between the native interface
of the Memory Controller and user applications
Table 1-9: Files In user_design/rtl/ui Directory
(1)
Name
ui_cmd.v
ui_rd_data.v
ui_wr_data.v
ui_top.v
Notes:
1. All file names are prefixed with the MIG core version number. For example, for the MIG 4.1 release module name
of ui_cmd in generated output is now mig_7series_v4_1_ui_cmd.
<component name>/user_design/xdc
Table 1-10 lists the modules in the user_design/xdc directory.
Table 1-10: Files in user_design/xdc Directory
Name
<component_name>.xdc
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
This module contains the Read leveling calibration logic (PHASER_IN
DQSFOUND calibration logic).
This module contains the memory initialization and overall master
state control during initialization and calibration.
This module contains the Read leveling Stage1 calibration logic
(Window detection with PRBS pattern).
This is the top-level module for the physical layer.
This module contains the write calibration logic.
This module contains the write leveling logic.
This PRBS module uses a many-to-one feedback mechanism for 2n
sequence generation.
Description
This is the user interface command port.
This is the user interface read buffer. It reorders read data returned from the
Memory Controller back to the request order.
This is the user interface write buffer.
This is the top-level of the Memory Controller user interface.
Description
This is the XDC for the core and the user design.
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(Table 1-9).
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