Table of Contents
Advertisement
CHAPTER 3 CPU AND CONTROL UNITS
3.2
Internal Architecture
The FR60Lite CPU is a high performance core based on the RISC architecture while
incorporating high-level function instructions for embedded applications.
■ Features
•
RISC architecture
Basic instructions: 1 instruction per cycle
•
32-bit architecture
32-bit general-purpose register × 16
•
4 Gbytes of linear memory space
•
Built-in multiplier
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
•
Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
•
Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit manipulation instruction
•
High coding efficiency
Basic instruction word length: 16 bits
•
Low-power consumption
Sleep mode and stop mode supported
•
Clock frequency divide ratio setting function
■ Internal Architecture
The FR60Lite CPU employs the Harvard architecture in which the instruction and data buses are independent
of each other.
The 32-bit↔16-bit bus converter is connected to a 32-bit bus (F-bus) to provide the interface between the
CPU and peripheral resources. The Harvard↔Princeton bus converter is connected to both of the I-bus and
D-bus to provide the interface between the CPU and the bus controller.
28
Advertisement
Table of Contents
