Fig. 2.26 Description Diagram For Internal Clock Mode Operation; Fig. 2.27 Flow Diagram For Timer Setting - Fujitsu MB89140 Series Hardware Manual

8/16-BIT TIMER
(TIMER 2 AND TIMER 3)
Counter clear
Set data value
Compare latch
Count value
0000
H
T2STR
T2IF

Fig. 2.26 Description Diagram for Internal Clock Mode Operation

Operation mode specification
T2STR = 1, T2IF = 0, T2IE = 1
HARDWARE CONFIGURATION
Description of Operation
(1) 8-bit internal clock mode
In the 8-bit internal clock mode, three internal clock inputs can be selected
by setting the clock source select bits (T2CS1 and T2CS0, T3CS1 and
T3CS0) of the timer control registers (T2CR and T3CR). The timer data reg-
isters (T2DR and T3DR) serve as interval time setting registers.
To start the timer, set the interval time to the timer data registers, write 1 at
the timer start bits (T2STR and T3STR) of the timer control registers to clear
the counter to 00 , and load the values of the timer data registers into the
H
compare latch. Then, counting starts.
When the values of the counter agree with the set value of the timer data
registers, the interval interrupt request flags (T2IF and T3IF) are set to 1. At
this time, the counter is cleared to 00
are reloaded into the compare latch, and counting is continued. If the inter-
rupt enable bits (T2IE and T3IE) are set to 1, an interrupt request is output to
the CPU. Assuming the set value of the timer data register is n and the se-
lected clock is φ, the interval time (T) can be calculated as follows.
T = φ
(n + 1) [µs]
Matched
T2IF = 0 (W)
Interval time setting
Timer start
T2IF = 1
Main program

Fig. 2.27 Flow Diagram for Timer Setting

2-52
, the values of the timer data registers
H
Matched Matched
T2IF = 0 (W) T2IF = 0 (W)
Interrupt processing
T2IF = 0 (W)